Some FlexRIO devices contain onboard DRAM that is directly accessible from the FPGA VI. LabVIEW supports two types of DRAM interfaces: FPGA memory items and socketed CLIP. You cannot use both FPGA memory items and socketed CLIP to access the same DRAM bank in an FPGA VI. Refer to your FPGA device's Specifications document to determine the available amount of onboard DRAM for your device.

Configuring DRAM

Refer to the following topics for information about configuring the DRAM for your FlexRIO device.

  • Configuring DRAM with FPGA Memory Items
  • Configuring DRAM with Socketed CLIP

For tips on how to use DRAM effectively in FlexRIO, refer to the Using DRAM Effectively with FlexRIO tutorial.

Disabling Synchronization Registers

The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers cause a delay in sending and receiving data or commands to and from the DRAM interface. For proper device operation, you must disable all synchronization registers for all DRAM interface signals and all input signals.

Note All NI PXI version 1.1 and later CLIP items and all NI PXI Express CLIP items automatically disable all synchronization registers.

Right-click a DRAM interface signal and select Properties from the shortcut menu to open the FPGA I/O Properties dialog box. Select Advanced Code Generation in the Category list to open the Advanced Code Generation page. Select 0 in the Number of Synchronizing Registers for Output Data box to disable all synchronization registers for that signal. Always disable synchronization registers for synchronous interfaces when proper operation depends on no latency.