The FlexRIO with Integrated I/O modules support both host-to-target streaming and target-to-host streaming through DMA channels that connect the host to your target. Use DMA streaming to allow the maximum throughput of data from your host application to be streamed to the target at high rates of speed.

The PXI FlexRIO Integrated I/O modules provide up to 60 DMA channels that can be accessed by your host. These channels can be used in a variety of ways to meet the needs of your application. The total overall bandwidth of the module limits your DMA use, whether you use 1 DMA channel or 60.

The maximum width of a DMA channel is 256 bits. To use the full width of the DMA channel to achieve maximum throughput, you can write an array of U64 elements into the DMA FIFO and configure the FIFO for multi-element read/write (four elements per read/write) to satisfy the 256 bit width. You can also write up to 1024 bits at a time from LabVIEW FPGA, and the Ready for Input connection throttles the connection to the FIFO to prevent overflow.

Theoretically, DMA throughput is maximized and is most consistent when the DMA FIFO buffer is sized as large as possible to absorb variations in the readiness of the host memory. However, sizing the FIFO larger consumes block RAM resources on the FPGA and increases the timing pressure on the FIFO. In order to sustain throughput through the PCIe bus to and from host memory, make the FIFO as large as you can successfully compile with. You can change the size of the FIFO by configuring the Requested Number of Elements for the FIFO in the project properties. You can validate the DMA sizing through benchmarking, and you can use VIs in the Streaming Design Library to monitor the health of a FIFO.

For more detailed information about using DMA, DMA best practices, and how to make design decisions on how to implement DMA in your application, refer to the Transferring Data Using Direct Memory Access topic in the LabVIEW FPGA Module User Manual.