FlexRIO devices support cycle-accurate simulation to aid in debugging your FPGA. Cycle-accurate simulation means that timing is precise, which allows for clock-by-clock analysis before the LabVIEW FPGA design is compiled to a bitstream. Cycle-accurate simulation can improve design quality and save development time. This topic describes the aspects of cycle-accurate simulation that are specific to FlexRIO devices.

To decrease cycle-accurate simulation compilation and execution times, FlexRIO devices use cycle-accurate simulation as their model fidelity. Cycle-accurate simulation timing is exactly the same as hardware timing, but the VHDL code is different than the code that the driver software implements on the target. For example, the onboard DRAM and corresponding DRAM controller on a FlexRIO device are both abstracted into a simulation model for cycle-accurate simulation. This abstraction means that the absolute delays may not match between simulation and actual execution, but the functional behavior is identical.

FPGA I/O Items

Cycle-accurate simulation can simulate all the FPGA I/O items for your FlexRIO device including PXI/PXI Express items, IO Module Status items, and Board IO items. In simulation, static values are provided as defaults for some FPGA I/O items. All other FPGA I/O items do not have default values. The following table lists the default values of some FPGA I/O items used in simulation.

FPGA I/O Item Default Value
IO Module Present TRUE
IO Module Power Good TRUE
IO Module Power Enabled TRUE
EEPROM Power Enabled TRUE
IO Module IO Enabled TRUE
Expected IO Module ID Matches expected ID of the currently configured FlexRIO adapter module
Inserted IO Module ID Matches expected ID of the currently configured FlexRIO adapter module
Device Temperature 25 °C (b0000000001100100, 1 LSB = 0.25 °C)
Clock100 PLL Unlocked FALSE (PXI Express devices only)

If you want to simulate something other than the default value, you can override these values by connecting your own stimulus inside the test bench.

Note You cannot change the value of the Clock100 PLL Unlocked signal in simulation.

Adapter Module Signals

To communicate with your adapter module, your FlexRIO FPGA module provides 66 general-purpose I/O (GPIO) signals and four clock signals (two Global clocks and IO Module Clock 0/1). You can configure these signals as you normally would in LabVIEW FPGA or with a stimulus model. If you configure these signals normally, refer to your adapter module documentation for information about how these signals and clocks work in your FlexRIO system. If you have a stimulus model for your FlexRIO adapter module, you can instantiate it in your test bench to imitate the functionality of your FlexRIO adapter module.

Note By default, the GPIO Enable signal for your device is TRUE.
Note You cannot access the I2C signals in cycle-accurate simulation.

DRAM

Cycle-accurate simulation supports DRAM functionality for FlexRIO devices that have onboard DRAM, but it limits the DRAM to a maximum of 1 MB. The following devices do not have onboard DRAM:

  • NI PXI-7951R
  • NI PXIe-7961R
  • NI PXIe-7971R