What Should I Do If Signals Are Distorted with a Bit Shift?

Symptom

During PCM acquisition, when the receiver (FPGA) in master mode generates the bit clock and the frame sync clock, the signals that the receiver acquires are distorted or have incorrect amplitude with a bit shift, as the following figures show. This issue also occurs during PCM generation when the receiver (DUT) in master mode generates clocks.

Figure 4. Distorted Signal with a Bit Shift (Endianness Set to LSB First)

Distorted Signal with a Bit Shift (Endianness Set to LSB First)

Figure 5. Distorted Signal with a Bit Shift (Endianness Set to MSB First)

Distorted Signal with a Bit Shift (Endianness Set to MSB First)

Figure 6. Bit-Shifted Signal with Incorrect Amplitude

Bit-Shifted Signal with Incorrect Amplitude

Note This issue is noticeable especially at higher bit clock rates when the bit clock period is less than 100 ns.

Root Cause

Cables cause propagation delays.

Solution

To compensate for cable propagation delays during PCM acquisition, set Latch Delay in the PCM input task to delay data latching by the FPGA. NI recommends a 50 ns delay at 12 MHz bit clock for 1 m cables.

To compensate for cable propagation delays during PCM generation, set Generation Timing Offset to advance data generation. NI recommends a 50 ns generation offset at 12 MHz bit clock for 1 m cables.

The following figure shows a correct signal after you set Latch Delay or Generation Timing Offset.


Correct Signal