Acquiring and Generating PCM Signals of Different Serial Audio Interface Types

You must complete specific API configurations to acquire and generate PCM signals of each serial audio interface type that has unique timing logic. You can use the following example API configurations or modify API controls based on your test needs.

Introduced in Digital Audio Acquisition and Generation Toolkit 2023 Q3

I2S

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Falling
Channel Count Per Frame 2
Channel Length 32
Bit Depth 24
Channel 0 Offset 1
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length 64
Frame Sync Pulse Width 32
Bit Clock Edge Sync Falling

The following figure demonstrates the timing logic of I2S when you configure API controls as the previous table shows.


Timing Logic of I2S

Left-Justified

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Rising
Channel Count Per Frame 2
Channel Length 32
Bit Depth 24
Channel 0 Offset 0
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length 64
Frame Sync Pulse Width 32
Bit Clock Edge Sync Falling

The following figure demonstrates the timing logic of left-justified when you configure API controls as the previous table shows.


Timing Logic of Left-Justified

Right-Justified

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Rising
Channel Count Per Frame 2
Channel Length 32
Bit Depth 24
Channel 0 Offset 0
Endianness MSB First
Data Justification Right Justified
Frame Sync Clock Control Frame Length 64
Frame Sync Pulse Width 32
Bit Clock Edge Sync Falling

The following figure demonstrates the timing logic of right-justified when you configure API controls as the previous table shows.


Timing Logic of Right-Justified

4-Channel TDM

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Rising
Channel Count Per Frame 4
Channel Length 32
Bit Depth 24
Channel 0 Offset 0
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length 128
Frame Sync Pulse Width 64
Bit Clock Edge Sync Falling

The following figure demonstrates the timing logic of 4-Channel TDM when you configure API controls as the previous table shows.


Timing Logic of 4-Channel TDM

6-Channel TDM

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Falling
Channel Count Per Frame 6
Channel Length 32
Bit Depth 32
Channel 0 Offset 0
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length 192
Frame Sync Pulse Width 96
Bit Clock Edge Sync Falling

8-Channel TDM

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Falling
Channel Count Per Frame 8
Channel Length 32
Bit Depth 24
Channel 0 Offset 0
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length 256
Frame Sync Pulse Width 128
Bit Clock Edge Sync Falling

S/PDIF

API Control Value
PCM Data Configuration Frame Sync Edge for Channel 0 Depending on test needs
Channel Count Per Frame Depending on test needs
Channel Length Depending on test needs
Bit Depth 16
Channel 0 Offset 4
Endianness MSB First
Data Justification Left Justified
Frame Sync Clock Control Frame Length Depending on test needs
Frame Sync Pulse Width Depending on test needs
Bit Clock Edge Sync Depending on test needs

The following figure demonstrates the timing logic of S/PDIF when you configure API controls as the previous table shows.


Timing Logic of S/PDIF

If you set Channel 0 Offset to 0 and Bit Depth to 24, the timing logic of S/PDIF changes as the following figure shows.


Timing Logic of S/PDIF

Note Besides the API controls described in the previous tables, other controls, such as Bit Clock rate, Clock Mode, frequency, gain, phase, and microphone sensitivity, also affect output waveforms.