To run a project on an FPGA target with an NI 985x C Series module, you need an FPGA bitfile (.lvbitx). The FPGA bitfile is downloaded to the FPGA target on the execution host. A bitfile is a compiled version of an FPGA VI. FPGA VIs, and thus bitfiles, define the CAN, analog, digital, and pulse width modulation (PWM) inputs and outputs of an FPGA target. The Automotive Diagnostic Command Set does not include FPGA bitfiles for any FPGA target. Refer to the LabVIEW FPGA Module documentation for more information about creating FPGA VIs and bitfiles for an FPGA target.

The default FPGA VI is sufficient for a basic Automotive Diagnostic Command Set application. However, in some situations you may need to modify the existing FPGA code to create a custom bitfile. For example, to use additional I/O on the FPGA target, you must add these I/O to the FPGA VI. You must install the LabVIEW FPGA Module to create these files.

Modify the FPGA VI according to the following guidelines:

  • Do not modify, remove, or rename any block diagram controls and indicators named __CAN0 Rx Data, __CAN0 Rx Ready, __CAN0 Tx Data Frame, __CAN0 Tx Ready, __CAN0 Bit Timing, __CAN0 FPGA Is Running , __CAN0 Start, __CAN0 FIFO Full, or __CAN0 FIFO Empty. If you intend to use multiple CAN 985x modules on your FPGA, you need to duplicate and rename all controls and indicators accordingly.
  • Do not modify the CAN read and write code except to filter CAN IDs on the receiving side to minimize the amount of CAN data transfers to the host.
  • As you create controls or indicators, ensure that each control name is unique within the VI.

Refer to the LabVIEW FPGA Module documentation for more information about creating FPGA VIs and bitfiles for an FPGA target.

When using ADCS on CompactRIO with an NI 985x C Series module, the interface name is based on the bitfile you use and the interface name you set. For example, MyInterface@MyBitfile.lvbitx, CAN@lvbitfile.lvbitx, or CAN0@mybitfile.lvbitx.

The interface name you use must be part of all parameters in the FPGA code for the CAN communication. Also, the ADCS needs the interface name for correct functionality.

If you define the interface name to be CAN0, you must name the parameters as follows:

  • __CAN0 Rx Data
  • __CAN0 Rx Ready
  • __CAN0 Tx Data Frame
  • __CAN0 Tx Ready
  • __CAN0 Bit Timing
  • __CAN0 FPGA Is Running
  • __CAN0 Start
  • __CAN0 FIFO Full
  • __CAN0 FIFO Ready

In addition, you need to set the name of the internally used FIFO to __CAN0 FIFO (the FIFO is set to U32, 1029 elements, target scoped, and block memory).

After recompiling your FPGA VI, copy the bitfile to the root directory of your CompactRIO controller and specify the bitfile in the interface name. Or copy the file to any location on the CompactRIO controller and specify an absolute path or path relative to the root for the bitfile.

If you are using an NI-XNET 986x C Series module on your CompactRIO target, you need to start an FPGA VI on the target before accessing the port with ADCS. Refer to the Getting Started with CompactRIO section in the NI-XNET Hardware and Software Help for more information about compiling the FPGA VI. When the VI is running, you can access the NI 986x module as you would program on a Windows or PXI LabVIEW Real-Time target.