The following topics describe how to graphically define the internal structure of a PLD (programmable logic device). They also describe how to export the PLD design to VHDL files or programming files, and how to program a connected PLD.

Some of the described features may not be available in your edition of Multisim. Refer to Features by Tier for more information.

Multisim PLD supports:

  • Xilinx ISE—versions 12.x, 13.x and versions 14.1 through 14.7.
  • NI FPGA ISE—versions 13.4, 14.4 and 14.7.
  • Xilinx Vivado—versions 2013.1, 2013.2, 2013.3, 2013.4, 2014.1, 2014.2, 2014.3, 2014.4, 2015.1, 2015.2, 2015.3, 2015.4, 2016.1, 2016.2, 2016.3, and 2016.4.
  • NI FPGA Vivado—versions 2013.4, 2014.4, 2015.2, 2015.3, 2015.4 and 2016.2.

This topic refers to education-specific features of Multisim.