A PLD schematic defines the internal logical behavior of a PLD and the interface to external logical connections. PLD schematics can be exported to VHDL files, a programming file, or used to program a connected PLD (FPGA).

A PLD schematic contains specialized components that define the operation of the individual logic blocks of the PLD.

These PLD components include both SPICE models and VHDL export data. This allows the components to be simulated in Multisim, and then exported with VHDL-only data.

  The PLD components are not compatible with older MultiVHDL components and models. Co-simulation between Multisim and MultiVHDL was discontinued with version 11 of Circuit Design Suite.

Some additional diagnostic components such as probes and Multisim instruments can also be placed on a PLD schematic. These components do not change the PLD topology and are not exported when an Export to PLD command is executed.

The PLD schematic:

  • restricts the components that can be placed to those that can be mapped for VHDL export, and to special diagnostic components.
  • has special port connectors that map the external nets to internal signals and identify the signal modes.
  • may enable programming of a connected PLD.
  • may enable generation and saving of a programming file.
  • enables export to VHDL.

      You cannot export a PLD schematic to Ultiboard, or any other PCB layout application. The PLD device in a Multisim schematic has no layout information.

This topic refers to education-specific features of Multisim.