DDR 1X (100 Mbps):
To demonstrate DDR, the example below will start with a double data rate interface running at 100 Mbps, with a vector period of 10 ns. The data would only need to change once every 10 ns, so it could simply be described with a NR pattern with the data and clock, with alternating 1’s and 0’s for the clock. Figures 3 and 4 show the timing sheet and pattern used, respectively, while Figure 4 shows the Digital Scope after bursting the pattern.
DDR 1X (200 Mbps):
However, if the goal is to run the DDR interface faster than 100 Mbps, you will need to change out timesets to describe the data, even though the digital pattern instrument might technically be capable of describing the waveform by using RL and RH formats. Depending on how many pins there are, this process could be difficult and confusing. The example below is a simple demonstration of this method. This method is not recommended. Instead the 2X edge multiplier feature should be used as shown in the DDR 2X (200 Mbps) section below.
Figure 7 depicts a new pattern demonstrating DDR, but it is being run at 200 Mbps without using the edge multiplier feature. As shown in Figure 6, the clock can be described using an RL format, which is simple. However, the return format for the data must be chosen based on the data to be transmitted. Figure 8 shows the Digital Scope after bursting the pattern.
So, while this is possible, it is confusing since it is necessary to change the format on a cycle by cycle basis. If there were more pins, then problems such as not having enough time sets become more likely. Additionally, if source memory was used, the digital pattern instrument would not have a way of generically supporting it, since the time sets cannot change based on the data.
DDR 2X (200 Mbps):
The 2X edge multiplier feature was added to address this issue. It enables describing multiple data drive values within a single vector cycle. The same example from above is repeated here, this time using the 2X edge multiplier feature to make it much easier to describe. Figure 9 and 10 show the timing sheet and pattern used, respectively. Figure 11 shows the Digital Scope after bursting the pattern.
SDR 2X (133 Mbps):
While the same techniques could be used for getting the data to update at up to 200 Mbps, this would require a bit rate on the clock of 400 Mbps, which is too fast for the digital pattern instrument (unless the consequences described above are acceptable for your application). With a minimum pulse width of 3.75 ns, the best the digital pattern instrument can do is a clock bit rate of 266 Mbps, which is a 133 MHz clock and 133 Mbps data. Figure 12 shows the pattern and Figure 13 shows the Digital Scope after bursting the pattern. Note that the period used in this example changed from 10 ns to 15 ns in order to fit timing requirements.