This document provides tutorials on how to import an example model or algorithm written in MATLAB® or Simulink®, generate VHDL using HDL Coder™, import into LabVIEW FPGA, and test on NI FPGA hardware connected to real-world inputs and outputs. NI recommends reading this document for additional context on LabVIEW integration options and using HDL Coder before following the tutorials.
1. Create a VHDL export with HDL Coder and MATLAB or Simulink:
2. HDL Coder and LabVIEW FPGA: Importing HDL Coder Exports in LabVIEW FPGA
3. HDL Coder and LabVIEW FPGA: Creating LabVIEW FPGA Host Code and Testing with Simulation
The Software versions below were used in the creation of the tutorials. Other versions may work with differences in appearance.
Before beginning the integration of a design, you need to make several choices on how to integrate the function in LabVIEW FPGA. NI recommends performing research on these options using the available documentation to best make an educated decision. This section summarizes some of these options as a starting point.
The LabVIEW FPGA Module supports several interface types. While these may not be required depending on the requirements of a specific design, they make the integration of external functions into LabVIEW FPGA more robust and portable. The following are a subset of possible options:
For the tutorials in this series, the Valid In and Valid Out option will be used. This option is the simplest to implement as it requires minimal design changes to existing functions and minimal additional signals. However, this option also assumes nothing stalls the execution of the design. Specifically:
When integrating functions or working with a design that does not meet these requirements, NI recommends using the handshaking interface. For more information on other integration options, refer to the following resources:
The LabVIEW FPGA Module provides two main methods to integrate external IP: Component-Level Intellectual Property (CLIP) and the Intellectual Property Integration (IP Integration) Node, each of which has different use cases, advantages, and disadvantages. Refer to the following guidelines for information about choosing between the two methods:
The above is simply a high-level overview. More comparisons and best practices can be found in The NI LabVIEW High-Performance FPGA Developer's Guide and the LabVIEW FPGA Module Help. NI recommends referring to Integrating Third-Party IP (FPGA Module) for a complete comparison between the options and a list of supported file types.
In this tutorial series, the simple FIR Filters will be used to demonstrate the process. This type of design aligns more closely with the functional or algorithmic nature of the IP Integration Node and will follow that workflow. In fact, most HDL Coder exports fit this functional paradigm and should be imported using the IP Integration Node.
While many functions may be exported to an HDL representation using HDL Coder, only some Simulink blocks and MATLAB functions are supported by the export process. In addition, it’s important to consider designs from the hardware context. A design that runs efficiently in a software implementation may not translate well to the physical hardware representation used by FPGA devices. NI recommends reviewing the Getting Started with HDL Coder documentation before attempting to create a custom function or model for HDL code generation.
HDL Coder provides several options for code generation targets. Of these, two options result in code that is fully usable in LabVIEW FPGA:
The tutorials demonstrating the process will focus on the Generic ASIC/FPGA option as it does not require any additional software or knowledge of AXI interfaces. For more information on the IP Core Generation workflow, refer to IP Core Generation in the official HDL Coder documentation.
Note: If you use the IP Core Generation option, NI recommends using the Xilinx Vivado version that installs with the LabVIEW FPGA Module Xilinx Compilation Tool for Vivado. This ensures that the toolchain used is the same one that LabVIEW FPGA uses for FPGA compilation. The path to this tool is typically as follows: <LabVIEW FPGA installation drive>\NIFPGA\<Vivado version>\bin\vivado.bat.
MATLAB functions written for HDL Coder export have differences and limitations when compared to a typical MATLAB function. While both are similarly formatted, functions which will be used with HDL Coder should be written with the understanding that the code will be converted to an HDL representation. This approach helps to ensure that the HDL export can meet performance requirements – such as speed or resource usage – once imported into LabVIEW FPGA.
When designing or converting a MATLAB function for HDL code generation, keep the following guidelines in mind:
Simulink designs to be exported by HDL Coder should follow the recommended HDL Modeling Guidelines for models to ensure that everything is supported and exported efficiently. While it is possible to export Simulink code without keeping these in mind, the export will be more efficient if you take the hardware architecture into consideration during the design process.
Keep the following recommendations in mind when creating and modifying Simulink models for HDL code generation.
When exporting a design to HDL using HDL Coder, you can manage the process with either the HDL Workflow Advisor or through direct functions and scripting. NI recommends starting with the HDL Workflow Advisor when exporting code for the first time to better understand the available options. For an example of how to script HDL Coder, see Generate HDL Code from MATLAB Code Using the Command Line Interface.