The following is an example of how to verify timing on the RMC connector with an SPI interface. SPI is a very common and versatile protocol, and this example assumes a working knowledge of SPI protocol requirements.
This example calculates the timing margin with a 10 MHz SPI CLK. If there is a positive margin for each constraint, then timing is successfully being met. For any SPI application, the easiest solution to a negative margin is to slow down the SPI CLK.
The Single-Board RIO controller is acting as the SPI master, and the SPI slave for this example is an SPI EEPROM. The data lines are updated on the falling edge of the SPI CLK and registered at the other device on the rising edge. You need the EEPROM’s timing specifications to verify timing, and example specifications are shown in Table 3. For a different SPI slave device, you need to obtain the information in Table 3 from that device's data sheet.
||MISO Clock to Out
||CLOAD = 100pF
Table 3. Example EEPROM SPI Timing Specifications
SPI devices also have timing requirements related to the slave select line. These are generally not the limiting factor in SPI performance; however, you should account for them in an actual design. Timing analysis for slave select is similar to MOSI.
The slave device’s setup is the minimum amount of time MOSI must be stable before the latching edge of SPI CLK to guarantee the current value is registered.
The slave device’s hold is the minimum amount of time MOSI must be stable after the latching edge of SPI CLK to guarantee the current value is registered.
MISO Clock to Out
Master In Slave Out (MISO) Clock to Out is the maximum time it takes the slave device to drive MISO after it has received the falling edge of SPI CLK. It is typically specified with a capacitive load. In this example, the load is 100 pF. This means the specification is valid as long as the load on MISO is less than or equal to 100 pF.
For calculating the MOSI setup margin, the maximum margin is half of the SPI CLK's period. This is because MOSI is updated on the one edge of SPI CLK and latched on the other. The Single-Board RIO controller's maximum skew must be subtracted from the margin because both MOSI and SPI CLK are DIO channels. The slave device's setup also reduces the margin. Finally, any skew between the SPI CLK and MOSI on the RMC should be removed from the margin. A skew of 1 ns is conservative for a well-designed RMC with point-to-point signal routing and trace length matching to 1 in.
MOSI Setup Margin = SPI_CLK_Period/2 – tSKEW – slaveSU – RMCSKEW
MOSI Setup Margin = 50 ns – 12 ns – 10 ns – 1 ns
MOSI Setup Margin = 27 ns
The calculation for the MOSI hold margin is similar to setup except the slave device's hold specification is used instead of its setup specification. Skew is still included since the skew may occur in either direction. Depending on the direction of the skew, it reduces either the setup or hold timing margin, but it should be included in both as a worst case.
MOSI Hold Margin = SPI_CLK_Period/2 – tSKEW – slaveHO – RMCSKEW
MOSI Hold Margin = 50 ns – 12 ns – 10 ns – 1 ns
MOSI Hold Margin = 27 ns
Figure 5. MOSI Timing at Slave Device
MISO setup margin is a round-trip calculation. It must include the time it takes the SPI_CLK to reach the slave device and the time it takes MISO to reach the RMC connector. tCO is the maximum time it takes the falling edge of SPI_CLK to arrive on the RMC connector. RMCSCLK_PROP_DELAY is the propagation delay on the RMC from the connector to the slave device. Next, the slave device's clock to out must be removed from the margin. Then, the propagation delay of MOSI from the slave device back to the RMC connector is subtracted. Finally, the setup time of the RMC connector must be met and therefore removed from the margin.
For the RMC propagation delays, 1 ns is used in this example. This number varies based on the design of the RMC. 1 ns is a conservative number for RMCs designed with 55 Ω trace impedance and trace lengths less than 4 in. Propagation delays for the Single-Board RIO controllers have already been accounted for in the RMC timing specifications.
MISO Setup Margin = SPI_CLK_Period/2 – tCO – RMCSCLK_PROP_DELAY – slaveCO – RMCMISO_PROP_DELAY – tSU
MISO Setup Margin = 50 ns – 19 ns – 1 ns – 20 ns – 1 ns – 6 ns
MISO Setup Margin = 3 ns
The MISO hold calculation is similar to the MOSI hold. This is because the worst case for hold removes many of the setup variables. Propagation delays help hold margin, so as a worst case they are assumed to be zero. The slave device's clock to out also increases hold margin, so it too is assumed to be zero. That leaves any skew between the SPI CLK and MISO signals that could reduce hold margin and the RMC connector's minimum hold time.
MISO Hold Margin = SPI_CLK_Period/2 – tSKEW – RMCSKEW – tHO
MISO Hold Margin = 50 ns – 12 ns – 1 ns – 4 ns
MISO Hold Margin = 33 ns
Figure 6. MISO Timing
Note: For any other synchronous interfaces, you should conduct similar calculations to ensure timing is met.