LabVIEW NXG 4.0 FPGA Module Bug Fixes


The following items are a subset of known issues fixed between LabVIEW NXG 3.1 FPGA Module and LabVIEW NXG 4.0 FPGA Module. If you have a Bug ID, you can search this list to validate that the issue has been fixed. This is not an exhaustive list of all bugs fixed in this release and does not capture bugs that were fixed in LabVIEW NXG.


Fixed Issue
572838 Reported Compile Duration may be incorrect after reconnecting to compilation
718663 A generic back-end compile error is thrown when compiling designs with DMA FIFOs or DRAM in clock domains of 500 MHz or greater. The case is not supported and a more descriptive error message has been added.
727385 I/O Constants are incorrectly renamed when a FAM associated with that I/O is removed and then re-added.
704962 Memory resources configured for LUT storage display a read latency of 1 cycle in the disabled drop-down configuration menu when the actual read latency is 0 cycles.


Glossary of Terms


  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).