ID | Fixed Issue |
---|---|
572838 | Reported Compile Duration may be incorrect after reconnecting to compilation |
718663 | A generic back-end compile error is thrown when compiling designs with DMA FIFOs or DRAM in clock domains of 500 MHz or greater. The case is not supported and a more descriptive error message has been added. |
727385 | I/O Constants are incorrectly renamed when a FAM associated with that I/O is removed and then re-added. |
704962 | Memory resources configured for LUT storage display a read latency of 1 cycle in the disabled drop-down configuration menu when the actual read latency is 0 cycles. |