MXI-Express compatibility issues can be roughly split into two categories:
- Not having enough resources/buses available.
- Having adequate resources/buses, but the BIOS is incapable of distributing them.
Therefore, the success of enumeration depends on the number of bus resources required by your PCIe/PXIe system, and the motherboard and BIOS version. This document will specifically address the first category, as the second category cannot be determined until the MXI-Express hardware is connected to the system.
There are several ways host computers allocate available bus resources that can impact how many are available for your system. Refer to the sections below for the most common types of PCIe structures and how resources are reserved in those systems. You can identify the PCIe structure by contacting the motherboard manufacturer or running the NI Resource Root Bus Utility described later in this document.
Single Root, Full Bus Range PCIe Structure
With a single root, full bus range PCIe structure, the host system can enumerate up to 256 PCIe buses, as shown in Figure 1. This includes all onboard devices and any expansion devices connected via PCI Express slots.
Figure 1: The host computer’s PCIe structure allows all buses to be enumerated.
The maximum number of buses available is 256, as stated in the PCI specification. In an ideal, compliant PCIe structure, all 256 of these buses would be on a single root complex, allowing for all buses to be enumerated regardless of bus topology. This is the best scenario for MXI-Express because it gives you the ability to connect several chassis in a daisy-chain configuration to the same PCI Express slot and significantly reduces the risk of incompatibility.
Artificially Limited PCIe Bus Range
To optimize boot-time performance for certain use cases, some motherboard vendors have limited the number of supported buses. It is not uncommon to find BIOSs that only allow for 64 or 128 PCI bus resources maximum across the entire PCI hierarchy.
In several cases, PXI may still enumerate correctly in a system with a limited PCIe bus range if the amount of required buses does not exceed the amount available. This limitation reduces the amount of PCIe/PXIe hardware that can be connected to the host computer. These systems are more likely to enumerate correctly when using a single chassis, and less likely to enumerate correctly as the complexity of the topology approaches the artificial limit of the host computer.
User-Selectable PCIe Bus Range
With a user selectable PCIe bus range, you can select the maximum number of buses available. Motherboard vendors provide this option to optimize performance in systems with less complex PCIe/PXIe hardwareome applications while still allowing for the flexibility of systems applications requiring a large number of buses. In this configuration, there are options such as 64 (usually default), 128, and 256 buses. This varies from computer to computer.
If available, make sure the BIOS settings are set to 256 bus numbers by consulting the motherboard user manual. If this setting is set to anything lower than 256, the system may or may not enumerate depending on how many bus resources are required by the attached system.
Multiple Root Buses
Some systems might allow for enough bus numbers for a PXI system, but these resources are split between two or more root buses or PCI Express slots. When this happens, only some of the bus resources are accessible via one PCI Express slot.
Figure 2 shows an example of a system that has 256 resources available, but the PXI system can take advantage of only 128 of these resources. If the system requires less than 128, then it will likely enumerate correctly. However, if the required resources exceed 128 (for example, several 18-slot chassis daisy-chained together), then it may fail to boot, only enumerate partially, or not enumerate at all.
Figure 2: Some systems split the available buses between two separate PCI Express slots.