This document contains the LabVIEW NXG 3.1 FPGA Module known issues that were discovered before and since the release of LabVIEW NXG 3.1 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The following items are known issues in LabVIEW NXG 3.1 FPGA Module.
| ID | Known Issue | |||||
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| 572838 Return | Reported Compile Duration may be incorrect after reconnecting to compilation If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document. Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.
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| 709263 Return | Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application Renaming an FPGA Application breaks associated Open FPGA VI Reference nodes referencing that application because the 'Rename and Update' dialog fails to automatically update the reference to use the new name. Workaround: Manually point the Open FPGA VI Reference to the correct FPGA Application.
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| 731891 Return | After software installation on LinuxRT targets, RIO server requires a manual restart or additional reboot If RIO server is enabled, remote FlexRIO devices may be targeted via the RIO server. After SW installation, this service is not fully configured and requires an additional reboot or manual restart to be fully setup. Workaround: After the required reboot post SW installation, reboot your target again. Alternatively, run the following commands to manually restart the service: /etc/init.d/nirioserver stop /etc/init.d/nirioserver start
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