LabVIEW FPGA Code Optimization

Overview

If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.

 

  Optimizing FPGA VIs for Speed and Size
If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.
  Optimizing FPGA VIs Using Pipelining
Pipelining is a technique you can use to increase the clock rate and throughput of an FPGA VI. Pipelined designs take advantage of the parallel processing capabilities of the FPGA to increase the efficiency of sequential code.
  Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining
Create customized I/O according to the specific requirements of your application. The pipelining and parallel code execution techniques described in this document allow you to optimize the performance for your FPGA code
  High CPU Usage When Reading Data from Target-to-Host DMA FIFOs
The Distributed System Manager that the Real-Time target's CPU usage nears 100%, when reading data into a LabVIEW Real-Time VI from an FPGA by using a Target-to-Host DMA FIFO.
 

Main Page: Everything You Need to Know About LabVIEW FPGA
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