PXI is built on CompactPCI, plus it offers additional Timing and Synchronization features. These additional features are implemented on the J2 connector of the boards (the P2 connector on the chassis):
NOTE: Slot 2 only has a local bus to its right because the left local bus is replaced with the Star Trigger.
All PXI chassis will make the features listed above available to the appropriate slots. It is up to the designer of the PXI board to route signals to the pins in the PXI backplane to take advantage of these features. Therefore, not all PXI boards will be able to use all of the timing and synchronization features available on the PXI backplane. Driver documentation and manual for your specific board should explain what features of the PXI backplane your board is capable of using.
|PXI E Series Signal||PXI Pin Name||PXI J2 Pin Number|
|RTSI Trigger (0...5)||PXI Trigger (0..5)||B16,A16,A17,A18,B18,C18|
|RTSI Trigger (6)||PXI Star||D17|
|RTSI Clock||PXI Trigger (7)||E16|
|Reserved||LBL(0..3)||C20, E20, A19, C19|
|Reserved||LBR(0..12)||A21, C21, D21, E21, A20, B20, E15, A3, C3, D3, E3, A2, B2|
This means that the PXI E series boards use PXI Trigger Lines 0,1,2,3,4,5,7, but not PXI Trigger Line 6. They are capable of reading the PXI Star Trigger Line and they cannot read the PXI Backplane Clock. The board has physical connections to some of the Local Bus Left lines (0 through 3) and to all the Local Bus Right lines. However, these lines are reserved by the driver, that is, NI-DAQ does not provide any function that allows the user to have access to these lines. With the NI-DAQmx driver, you can unreserve these lines in NI MAX under your chassis configuration. See the image below for a graphical representation of the table.
Note: MAX 3.x can automatically generate the correct PXISYS.INI file and place it in the correct location. For instructions on configuring your PXI system in Legacy Versions of MAX and information about PXISYS.INI, please refer to the Configuring Your PXI system in Legacy Versions of MAX. The PXI Specification defines 3 different types of slots in a PXI chassis:
The image below shows the type of slots of a NI PXI-1042 chassis with their numeration and glyphs:
It is necessary to save the PXISYS.INI file in the Systems directory in your computer so drivers can find it and read it. This way a driver can find out in what slot of the PXI chassis the board is installed. The drivers then will enable different circuits on the board depending on the slot that the board is located.
For example, a PXI-6608 counter board is capable of overriding the CLK10 signal in the PXI backplane. However the board will not override the CLK10 signal automatically. First the driver of the board, in this case NI-DAQ or NI-DAQmx, needs to read the PXISYS.INI file to find out if the board is installed in slot 2 of the PXI chassis. If this is correct, then the driver sends the appropriate commands to the PXI-6608 board to route the internal CLK10 signal to the PXI CLK10 signal.
|Available PXI BoardFunctions||NI PXI Boards||Additional Comments|
|Override the CLK10 signal|
|Phase Lock Loop (PLL) to the CLK10 signal|
|Drive the PXI Star Trigger|
|Receive the PXI Star Trigger|
|Read and Write to PXI Trigger Lines||Most NI PXI boards can read and write to the PXI Trigger lines||These PXI boards have 7 RTSI internal lines that are routed to the pins in the PXI backplane in the following way:|
|Use Local Bus||The only NI PXI boards that use the Local Bus are the ones that can control the SCXI portion of PXI Combo chassis (PXI-101x chassis) when installed in the right most slot of these chassis. The following are some of the capabilities of each type of board:|