DAQCM_Clock_Source Enumeration
- 已更新2023-02-21
- 閱讀時間為 3 分鐘
Specifies the source of the sample clock.
Namespace:
NationalInstruments.VeriStand.SystemDefinitionAPIAssembly: NationalInstruments.VeriStand.SystemDefinitionAPI (in NationalInstruments.VeriStand.SystemDefinitionAPI.dll) Version: 2013.0.0.0 (2013.0.0.0)
| Member name | Description |
|---|---|
| Onboard10MHzClock | The device's onboard 10 MHz clock. |
| PFI_0 | The PFI 0 terminal. |
| PFI_1 | The PFI 1 terminal. |
| PFI_10 | The PFI 10 terminal. |
| PFI_11 | The PFI 11 terminal. |
| PFI_12 | The PFI 12 terminal. |
| PFI_13 | The PFI 13 terminal. |
| PFI_14 | The PFI 14 terminal. |
| PFI_15 | The PFI 15 terminal. |
| PFI_2 | The PFI 2 terminal. |
| PFI_3 | The PFI 3 terminal. |
| PFI_4 | The PFI 4 terminal. |
| PFI_5 | The PFI 5 terminal. |
| PFI_6 | The PFI 6 terminal. |
| PFI_7 | The PFI 7 terminal. |
| PFI_8 | The PFI 8 terminal. |
| PFI_9 | The PFI 9 terminal. |
| RTSI_PXI_TRIG_0 | The RTSI 0 or PXI Trigger 0 terminal. |
| RTSI_PXI_TRIG_1 | The RTSI 1 or PXI Trigger 1 terminal. |
| RTSI_PXI_TRIG_2 | The RTSI 2 or PXI Trigger 2 terminal. |
| RTSI_PXI_TRIG_3 | The RTSI 3 or PXI Trigger 3 terminal. |
| RTSI_PXI_TRIG_4 | The RTSI 4 or PXI Trigger 4 terminal. |
| RTSI_PXI_TRIG_5 | The RTSI 5 or PXI Trigger 5 terminal. |
| RTSI_PXI_TRIG_6 | The RTSI 6 or PXI Trigger 6 terminal. |
| RTSI_PXI_TRIG_7 | The RTSI 7 or PXI Trigger 7 terminal. |
Remarks
 Note: |
|---|
The PXI trigger bus is the timing bus that connects PXI DAQ devices directly. The RTSI bus is the timing bus that connects PCI DAQ devices directly. These buses are functionally equivalent. |