Use this template as a starting point for applications where I/Q data is generated on a coprocessor and streamed to a VST for generation.

The Transmit template defines a potential starting point intended for adaptation to your specific use case. The interface options described below should be modified depending on the specific IP that is intended to be implemented with the txClip.

The Transmit VI operates as follows:

  1. Defines a 256-bit AXI4-Stream interface as an input for the txClip. This interface is connected to a Host-to-Target DMA and could be used to write data from the host application for use within the txClip.
  2. Defines a 512-bit AXI4-Stream interface as an output for the txClip. This interface is connected to the Write Data Stream VI method of the DLsc API and could be used to stream data from the coprocessor to a compatible VST and coprocessor.
    Note The 512-bit interface is connected to the U32 16SPC Write Data Stream Method and is only compatible with the PXIe-7903 using a compatible CLIP. This interface must be changed to a supported data width for all other FPGA Targets.
  3. Defines a 32-bit, 512 element AXI4-Lite Interface for the txClip. This interface is made available to the txClip and could be used to configure registers from the host.
  4. Defines an FPGA I/O Node interface for the txClip. This interface is connected to front panel controls and indicator on the block diagram and could be used to provide control/status of the specific net within the txClip.