Shaped Offset Quadrature Phase Shift Keying (SOQPSK) Modem Examples

Shaped Offset Quadrature Phase Shift Keying (SOQPSK) modulation is generated using a frequency modulator.

It belongs to a family of constant envelope Continuous Phase Modulation (CPM) waveforms. Because of the constant envelope, SOQPSK is efficient, with minimum spectral spreading. A SOQPSK symbol constellation may resemble the following figure.
Figure 14. SOQPSK Symbol Constellation

Refer to An Enhanced, Constant Envelope, Interoperable Shaped Offset QPSK (SOQPSK) Waveform for Improved Spectral Efficiency by Terrance J. Hill for more information about Shaped Offset Quadrature Phase Shift Keying.

Key Performance Parameters

Table 25. Modulator
Modulator FPGA IP single cycle timed loop clock rate 80 MHz
Modulator samples per cycle 2
Modulator samples per symbol 8
Maximum modulation rate 80M*(2/8) = 20 MSymbols/s
Table 26. Demodulator
Demodulator FPGA IP single cycle timed loop clock rate 160 MHz
Demodulator samples per cycle 1
Demodulator samples per symbol 8
Maximum demodulation rate 160M*(1/8) = 20 MSymbols/s

Modem Details

The modulated signal has a frame structure of preambles and payload, as shown in the following figure.

Figure 15. Modulated Signal Frame Structure

  • Four preambles at the beginning of each frame, for frequency offset and phase estimation.
  • Length of each preamble is fixed as 32 bit, due to the fixed structure of the correlator.
  • Configurable bit pattern.
  • Configurable payload length.
  • Fixed four samples/alpha symbol.

Modulator and Demodulator Configurations

Modulator:

  • Payload Length: symbol count after the preamble.
  • Preamble Symbol: The bit pattern used as preamble.
  • Symbol Rate.
  • NI-RFSG configurations: power level, carrier frequency, reference clock.

Demodulator:

  • Payload Length: symbol count after the preamble.
  • Preamble Symbol: The bit pattern used as preamble.
  • Symbol Rate.
  • NI-RFSA configurations: power level, carrier frequency, reference clock .

SOQPSK FPGA Modulator IP

A brief summary of the functioning of the modulator IP is shown in the following figure.

Figure 16. Modulator IP

  1. The bits are passed through the SOQPSK Precoder.
  2. The precoder output alpha (a) goes through the Symbol Mapping Block. The symbol mapping block implements a combination of Frequency Impulse Filtering and Frequency Modulation to generate the complex I/Q data, similar to the SOQPSK modulator described in Telemetry Standards, IRIG Standard 106-15.
  3. Additive White Gaussian Noise (AWGN) is added to the complex data created in the previous step.
  4. The noise added complex data is ready to be generated using the VST’s signal generator.

SOQPSK FPGA Demodulator IP

A brief summary of the functioning of the demodulator IP is shown in the following figure.

Figure 17. Demodulator IP

  1. The received complex baseband signal passes through a matched filter for the maximization of signal-to-noise ratio (SNR).
  2. The match filtered data passes through a preamble detection block. The preamble detection block also performs phase and frequency offset estimation.
  3. The estimated values of phase offset and frequency offset are used to correct the data.
  4. The corrected data are demodulated through an integrate and dump filter to give out recovered complex data as well as bits.

Bit Error Rate (BER) Measurements

The modem IP can perform bit error rate (BER) measurements based on the demodulated bits directly on the FPGA. This enables the system to compute BER real time while the data is being demodulated.

BER measurement is performed under certain assumptions:

  • Bits are part of a Pseudo Random Bit Sequence (PRBS).
  • PRBS resets at the end of the frame.
  • PRBS sequences of degrees: 7, 9, 10, 11, 15, 17, 18, 20, 21, 22, 23, and 25 are supported.
  • PRBS is based on a primitive trinomial of the form 1+xk+xn where tap (k) is selected based on the PRBS degree.

    The values of PRBS degree (n) and the tap (k) of the primitive trinomial are shown in the following table.

Table 27. PRBS Values
PRBS Degree (n) Primitive Trinomial Tap (k) Trinomial Form
7 6 1+x6+x7
9 5 1+x5+x9
10 7 1+x7+x10
11 9 1+x9+x11
15 14 1+x14+x15
17 14 1+x14+x17
18 11 1+x11+x18
20 17 1+x17+x20
21 19 1+x19+x21
22 21 1+x21+x22
23 18 1+x18+x23
25 22 1+x22+x25

Using the SOQPSK Modem Examples and Example Bitfiles

NI Data Link Test Framework provides SOQPSK modem examples and example bitfiles in the following locations:

  • SOQPSK modem examples: <LVAddons>\dltf\1\examples\Data Link Test Framework\Modems\SOQPSK
  • Example bitfiles for the SOQPSK modem examples: <LVAddons>\dltf\1\examples\Data Link Test Framework\Modems\SOQPSK\FPGA\FPGA Bitfiles