Configures the base, derived, and pulse generator clock signals you use in your application.

Drop this node onto the block diagram to launch the Configure Clock Type dialog box. In this dialog box, selecting from the list of available base and derived clocks produces a node that represents the clock. The clock name appears on the node. Selecting Pulse Generator produces a node that allows you to configure a custom clock. The units are shown under the pulse train picture on the node.

Example of Base or Derived Clock Node   Example of Pulse Generator Clock Node
  
  
  • Clock Output — Depending on the type of clock node you configure, the node can have two types of clock output terminals. The wire color indicates the type of clock signal.
    •   Clock Output (base and derived clocks only) supplies the clock signal to the asynchronous timing wire. The name of this terminal varies.
    •   Clock Output (pulse generator clock only) sends a series of periodic trigger events, or clock pulses, created from FGPA logic into an asynchronous timing wire. The name of this terminal varies. Click the red polarity indicator associated with this terminal to control whether the clock pulses are positive going () or negative going.
  • Period (pulse generator clock only) specifies the period of the clock pulses.
    Note You can wire a FIFO to the period terminal to create an arbitrary pulse train in which each pulse has a different period or duty cycle. If you wire a FIFO to this input terminal, write all your values into the FIFO-based asynchronous wires before you run the Clock node. Refer to the FIFO topic for more information about the FIFO underflow behavior.

User-Enabled Terminals

If you have associated a pulse generator clock with this node, this node has several terminals you can enable by selecting options from the node shortcut menu.

  • Timebase specifies the source for the timebase signal. Right-click the node and select Pulse Generation»Select Timebase»Use Timebase Terminal to enable the timebase terminal.
  • Pulse width specifies the pulse width of the clock pulses. Right-click the node and select Pulse Generation»Add Pulse Width Terminal to enable the terminal.
    Note You can wire a FIFO to the pulse width terminal to create an arbitrary pulse train in which each pulse has a different period or duty cycle. If you wire a FIFO to this input terminal, write all your values into the FIFO-based asynchronous wires before you run the clock node. Refer to the FIFO topic for more information about the FIFO underflow behavior.
  • Inverted output sends an inverted version of the clock output to an asynchronous timing wire. The name of this terminal varies. Right-click the node and select Pulse Generation»Add Inverted Output Terminal to enable the terminal.
  • Start trigger supplies a start trigger to the clock node. Click the polarity indicator () to toggle whether the Clock node detects a rising edge trigger (shown) or a falling edge trigger. Right-click the node and select Start Conditions»Add Start Trigger Terminal to enable the terminal. After you enable this terminal, you can choose to Respond to All Starts or to Create a Dataflow Start Trigger Input by right-clicking the node and selecting these options from the Start Conditions shortcut menu. Respond to All Starts is useful when a pulse Count Stop condition is configured and start triggers arrive at the start trigger terminal before the stop condition occurs.
  • first pulse delay specifies the duration to delay the first pulse. The units for the delay are the same as the timebase units shown on the node. Right-click the node and select Start Conditions»Add First Pulse Delay Terminal to enable the terminal.
  • Stop Condition — Right-click the node and select Stop Condition»Sample Count or Stop Condition»Trigger Edge to create one of the following two terminals.
    •   Stop Condition»Pulse Count Stop specifies the number of samples to acquire before stopping the ADC and waiting for another start trigger.
    •   Stop Condition»Digital Edge Stop Trigger supplies a digital edge stop trigger to the clock node. Click the polarity indicator () to toggle whether the Clock node detects a rising edge trigger (shown) or a falling edge trigger. After you enable this terminal, you can choose to Create a Dataflow Stop Trigger Input or Add Pulses After Stop Terminal by right-clicking the node and selecting these options from the stop Condition shortcut menu.

Clock Node Details

Select Configure Clock Type from the shortcut menu to relaunch the Choose Clock Type dialog box. In this dialog box, you can select from a list of base or derived clocks to associate with this node, or you can place this node in the pulse generator (custom clock) mode.

When you drop the clock node on the LabVIEW block diagram and configure it to create a pulse generator clock, the pulse units are automatically configured for microseconds. To change the pulse units, right-click the node and select Pulse Generation»Select Pulse Units from the shortcut menu.

Using the Pulse Editor

If you choose to create a pulse generator clock, you can use the Pulse Editor to configure the clock. To launch the Pulse Editor, right-click the node and select Pulse Generation»Use Editor. Using this editor, you can specify the following clock properties:

  • Duty cycle — Use the listbox control next to the Template waveform display to specify the duration of the logic high level, logic low level, and the number of times to repeat the pattern.
  • First pulse delay — Specify a duration to delay the first pulse.
  • Timebase source — Choose to either use the terminal on the clock node or the top-level clock for the clock domain.
  • Timebase units — Specify the units as either microseconds, milliseconds, timebase ticks, or you can choose a frequency and duty cycle for the clock.

You can wire a FIFO to the period or pulse width terminals to create an arbitrary pulse train in which each pulse has a different period or duty cycle. To use the FIFO in this way, write all your period or pulse width values into the FIFO-based asynchronous wires before you run the clock node. You can also use the Pulse Editor to create such a waveform, but it is a less flexible method because those waveforms cannot be changed at run-time. If you use a FIFO-based asynchronous wire to write period or pulse width values to a pulse generator-created clock node, wire the start trigger terminal to the clock node and only run the node after writing at least one value to the FIFO.