Use this page of the Feedback Node Properties dialog box to configure how LabVIEW implements the Feedback Node on an FPGA target.

This page includes the following components:

Option Description
First call initialization mux location

Specifies where the compiler places the multiplexer relative to the register that represents the Feedback Node on the FPGA. This placement affects the timing of FPGA applications.

This section is available only if you wire a value to the initializer terminal.

Note Placing the multiplexer after the register can significantly delay the combinatorial path after the Feedback Node, reducing the clock rate at which you can compile the FPGA VI. Use the compilation reports to experiment with the placement that works best for your application.
  • After register—Specifies that the compiler places the multiplexer after the register. Select this option if the FPGA VI has a long combinatorial path leading up to the Feedback Node but a short combinatorial path after the node.
  • Before register—Specifies that the compiler places the multiplexer before the register. Select this option if the FPGA VI has a short combinatorial path leading up to the Feedback Node but a long combinatorial path after the node.
  • Auto—Auto placement (default)—Specifies that the compiler places the multiplexer before the register if you wire a constant value to the initializer terminal. If you do not wire a constant value to this terminal, the compiler places the multiplexer after the register. You must place the constant in the same VI as the Feedback Node.
Compile or load initialization option(s) Compile or load initialization option(s)

Ignore reset—Specifies whether this Feedback Node initializes if the FPGA VI resets.Placing a checkmark in this checkbox has the following implications:

  • This node does not initialize if the FPGA VI resets.
  • The node initializes the next time you download the FPGA VI to the FPGA target. Ensure the application does not depend on the value this Feedback Node returns on the first call after resetting the FPGA VI.
  • LabVIEW removes the reset from the underlying register instantiations, which gives the compiler the option to implement the delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.