Testing Communication between the Host VI and an FPGA VI

To complete this task, you need the FPGA VI and the host VI you want to communicate between.

You can run FPGA code on the host computer to test the logic of the code without investing the time to compile it. Testing the communication between the host VI and the FPGA VI, on the host computer, saves time and makes it easier to repeat tests until you are ready to deploy to the FPGA.

What to Use

What to Do

Create the following diagram to communicate with the FPGA VI from a host VI.

Customize the gray section for your unique programming goals.


1378

1378 To specify the FPGA bitfile you want to deploy to the target, complete the following steps:
  1. On the diagram, select the Open FPGA Reference node.
  2. On the Item tab, in the Mode section, select Run bitfile on hardware.
  3. In the File list, select a bitfile within your project or select Dynamic reference and wire the bitfile path to the bitfile path input.
  4. Wire the address of the FPGA target to device name.
When you run this host VI, a reference to the FPGA application associated with the bitfile you selected opens and runs on the FPGA target you specify.
1378 When testing communication between a host VI and the FPGA VI, use test code that mirrors the communication that you want to occur when you actually deploy the FPGA VI. Use the FPGA Host Interface nodes to communicate with code on an FPGA and in simulation on the host computer.

In the diagram above, one of the ways the host VI and the FPGA VI communicates is through a DMA FIFO using the Write DMA FIFO and Read DMA FIFO nodes. When this host VI runs, the host VI and the FPGA VI write data to and read data from a block of memory on the host that simulates a FIFO on the FPGA.

Note The host VI cannot simulate FPGA Host Interface nodes that perform hardware-specific functions, such as the Download FPGA VI node or the P2P Streaming nodes.
1378 Use the Close FPGA VI Reference node to close every reference the Open FPGA Reference node creates. If you do not close the reference, the FPGA VI runs indefinitely until you click the Abort button in the FPGA VI.

Examples

Search within the programming environment to access the following installed example: FPGA Host Interface.