PXIe-5108 Specifications

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Updated2025-11-26
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PXIe-5108 Specifications

These specifications apply to the PXIe-5108 with 4 channels and the PXIe-5108 with 8 channels.

Revision History

Version	Date changed	Description
379215A-01	August 2025	Initial release.

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Definitions

Warranted Specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Specifications account for measurement uncertainties, temperature drift, and aging. Specifications are ensured by design or verified during production and calibration.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

Typical—describes the performance met by a majority of models.

Nominal—describes an attribute that is based on design, conformance testing, or supplemental testing.

Values are Typical unless otherwise noted.

Conditions

Specifications are valid under the following conditions unless otherwise noted.

All vertical ranges
All bandwidths and bandwidth limiting filters
Sample rate set to 250 MS/s
Onboard sample clock locked to onboard reference clock
PXIe-5108 module warmed up for 15 minutes at ambient temperature.^[1]¹ Warm-up begins after the chassis and controller or PC is powered, the PXIe-5108 is recognized by the host, and the PXIe-5108 is configured in NI-SCOPE. Self-calibration is recommended following the specified warm-up time.
Calibration IP used properly.

Warranted specifications are valid under the following conditions unless otherwise noted.

Ambient temperature range of 0 °C to 45 °C
Chassis configured:^[2]² For more information about cooling, refer to your chassis documentation and the Maintain Forced-Air Cooling Note to Users.
- PXI Express chassis fan speed set to HIGH
- Foam fan filters removed if present
- Empty slots contain PXI chassis slot blockers and filler panels
External calibration cycle maintained
External calibration performed at 23 °C±3 °C

Typical specifications are valid under the following conditions unless otherwise noted.

Ambient temperature range of 0 °C to 45 °C

Nominal and Measured specifications are valid under the following conditions unless otherwise noted.

Room temperature, approximately 23 °C

PXIe-5108 Front Panel

Figure 1. PXIe-5108 (4 Channel) and PXIe-5108 (8 Channel) Front Panel

Table 1. Connectors
Signal	Connector Type	Description
CH<0..7>	SMB	Analog input connection; digitizes data and triggers acquisitions
AUX 0	MHDMR	Sample Clock or Reference Clock input, Reference Clock output, bidirectional digital PFI, and 3.3 V power output

PXIe-5108 Pinout

Use the pinout to connect to terminals on the PXIe-5108.

Figure 2. PXIe-5108 AUX 0 Connector Pinout

Table 2. AUX 0 Connector Pin Assignments
Pin	Signal	Signal Description
1	GND	Ground reference for signals
2	CLK IN	Used to import an external Reference Clock or Sample Clock
3	GND	Ground reference for signals
4	GND	Ground reference for signals
5	CLK OUT	Used to export the Reference Clock
6	GND	Ground reference for signals
7	GND	Ground reference for signals
8	AUX 0/PFI 0	Bidirectional PFI line
9	AUX 0/PFI 1	Bidirectional PFI line
10	GND	Ground reference for signals
11	AUX 0/PFI 2	Bidirectional PFI line
12	AUX 0/PFI 3	Bidirectional PFI line
13	GND	Ground reference for signals
14	AUX 0/PFI 4	Bidirectional PFI line
15	AUX 0/PFI 5	Bidirectional PFI line
16	AUX 0/PFI 6	Bidirectional PFI line
17	AUX 0/PFI 7	Bidirectional PFI line
18	+3.3 V	+3.3 V power (200 mA maximum)
19	GND	Ground reference for signals

PXIe-5108 SCB-19 Pinout

You can use the SCB-19 connector block to connect digital signals to the AUX 0 connector on the PXIe-5108 front panel. Refer to the following figure and table for information about the SCB-19 signals when connected to the AUX 0 front panel connector.

Table 3. SCB-19 Signal Descriptions
Pin	Signal	Signal Description
1	PFI 0	Bidirectional PFI line
2	PFI 1	Bidirectional PFI line
3	PFI 2	Bidirectional PFI line
4	PFI 3	Bidirectional PFI line
5	NC	No connection
6	CLK IN	Used to import an external reference clock or sample clock
7	NC	No connection
8	CLK OUT	Used to export the reference clock
9	PFI 4	Bidirectional PFI line
10	PFI 5	Bidirectional PFI line
11	PFI 6	Bidirectional PFI line
12	PFI 7	Bidirectional PFI line
13	+3.3 V	+3.3 V power (200 mA maximum)
14 to 26	GND	Ground reference for signals

Mini-HDMI Breakout to SMA Cable Assembly Pinout

The mini-HDMI breakout to SMA cable assembly connects the AUX 0 MHDMR front panel connector of the PXIe-5108 oscilloscope to the two SMA PFI lines of up to four PXIe-5108 waveform generators within a PXIe-5108 to enable waveform-synchronous measurements.

Figure 3. Mini-HDMI Breakout to SMA Cable Assembly

Table 4. Mini-HDMI Breakout to SMA Cable Assembly Signal Descriptions
Item in Figure	Label	Connector	Description
1	MINI-HDMI BREAKOUT TO 8 SMA	Mini-HDMI (m)	Interface to PXIe-5108 AUX 0 interface connector^[3]³ Mini-HDMI and MHDMR are equivalent connectors.
2	PFI 0	SMA (m)	Bidirectional PFI line.
3	PFI 1	SMA (m)	Bidirectional PFI line.
4	PFI 2	SMA (m)	Bidirectional PFI line.
5	PFI 3	SMA (m)	Bidirectional PFI line.
6	PFI 4	SMA (m)	Bidirectional PFI line.
7	PFI 5	SMA (m)	Bidirectional PFI line.
8	PFI 6	SMA (m)	Bidirectional PFI line.
9	PFI 7	SMA (m)	Bidirectional PFI line.

Refer to the installation procedures for the PXIe-5108 to learn how to correctly connect all mini-HDMI breakout to SMA cable assemblies in your system.

PXIe-5108 AUX 0 Breakout Cable to 6 BNCs Pinout

You can use the AUX 0 Breakout Cable to 6 BNCs to connect digital signals to the AUX 0 connector on the PXIe-5108 front panel. Refer to the following figure and table for information about the AUX 0 Breakout Cable to 6 BNCs signals when connected to the AUX 0 front panel connector.

Table 5. AUX 0 Breakout Cable to 6 BNCs Signal Descriptions
Signal	Connector Type	Description
CLK IN	BNC female	Used to import an external reference clock
CLK OUT		Used to export the reference clock
PFI 0		Bidirectional PFI line
PFI 1		Bidirectional PFI line
PFI 2		Bidirectional PFI line
PFI 3		Bidirectional PFI line

Vertical

Analog Input

Table 6. Analog input specifications
	Number of channels	Input type	Connectors
PXIe-5108 (4 CH)	Four (simultaneously sampled)	Referenced single-ended	SMB, ground referenced
PXIe-5108 (8 CH)	Eight (simultaneously sampled)	Referenced single-ended	SMB, ground referenced

Impedance and Coupling

Input impedance

50 Ω ±1.5%, typical

1 MΩ ±0.5%, typical

Input capacitance (1 MΩ)

16 pF ±1.2 pF, typical

Input coupling

Figure 4. 50 Ω Voltage Standing Wave Ratio (VSWR), Measured

Figure 5. 50 Ω Input Return Loss, Measured

Voltage Levels

Table 7. 50 Ω FS Input Range and Vertical Offset Range
Input Range (V_pk-pk)	Vertical Offset Range (V)
0.2 V	±0.5
0.7 V	±0.5
1.4 V	±0.5
5 V	±2.5
10 V ^[4]⁴ Derated to 5 V_pk-pk for periodic waveforms with frequencies below 100 kHz.	0

Table 8. 1 MΩ FS Input Range and Vertical Offset Range
Input Range (V_pk-pk)	Vertical Offset Range (V)
0.2 V	±0.5
0.7 V	±0.5
1.4 V	±0.5
5 V	±4.5
10 V	±4.5
40 V	±20
80 V	0

Maximum input overload
50 Ω	7 V RMS with \|Peaks\| ≤10 V
1 MΩ	\|Peaks\| ≤42 V

Notice Signals exceeding the maximum input overload may cause damage to the device.

Accuracy

Table 9. Resolution
Resolution	14 bits

Table 10. DC Accuracy
50 Ω	±[(0.45% × \|Reading - Vertical Offset\|) + (0.4% × \|Vertical Offset\|) + (0.05% of FS) + 0.4 mV], warranted
1 MΩ, 40 V_pk-pk range	±[(0.45% × \|Reading - Vertical Offset\|) + (0.5% × \|Vertical Offset\|) + (0.05% of FS) + 0.4 mV], warranted
1 MΩ, all other ranges	±[(0.45% × \|Reading - Vertical Offset\|) + (0.4% × \|Vertical Offset\|) + (0.05% of FS) + 0.4 mV], warranted

Note Within ± 5 °C of self-calibration temperature. Accuracy is warranted only when using DC input coupling. DC specifications apply only in any of the following situations:

The sample rate is set to 250 MS/s.
NI-SCOPE is 21.0 or later, Sample Clock Time Base Source is set to VAL_ONBOARD_CONFIGURABLE_RATE_CLK, and the Sample Clock Timebase Rate is set to 200 MS/s or 150 MS/s.

In all other situations, derate DC accuracy by the DC accuracy sampling drift.

Table 11. DC drift
DC drift	±[(0.010% × \|Reading - Vertical Offset\|) + (0.003% × \|Vertical Offset\|) + (0.006% of FS)] per °C

Note Used to calculate errors when onboard temperature changes more than ±5 °C from the self-calibration temperature.

Table 12. AC amplitude accuracy
50 Ω	±0.15 dB at 50 kHz, warranted
1 MΩ, 40 V_pk-pk and 80 V_pk-pk ranges	±0.25 dB at 50 kHz, warranted
1 MΩ, all other ranges	±0.15 dB at 50 kHz, warranted

Table 13. Conversion error rate
250 MS/sec	<1 × 10^-10
200 MS/sec	<1 × 10^-15
150 MS/sec	<1 × 10^-20

Note A conversion error is defined as deviation greater than 0.6% of full scale.

Table 14. Crosstalk
Frequency	Level
Frequency	50 Ω	1 MΩ, 0.2 V_pk-pk to 10 V_pk-pk Range	1 MΩ, 40 V_pk-pk Range
1 MHz	-75 dB	-75 dB	-65 dB
50 MHz	-75 dB	-75 dB
100 MHz	-70 dB	-70 dB

Note Measured on one channel with test signal applied to another channel, with the same range setting on both channels.

Notice This device may experience increased peak to peak noise when connected cables are routed in an environment with radiated or conducted electromagnetic interference. To limit the effects of this interference and to ensure that this device functions within specifications, take precautions when designing, selecting, and installing measurement probes and cables.

Bandwidth and Transient Response

Table 15. Bandwidth (-3 dB), Warranted
Input Impedance	Input Range (V_pk-pk)	Bandwidth
50 Ω	0.2 V	99 MHz
50 Ω	All other input ranges	100 MHz
1 MΩ ^[5]⁵ Verified using a 50 Ω source and 50 Ω feedthrough terminator.	All input ranges	98 MHz

Note Normalized to 50 kHz.

Table 16. Bandwidth-limiting filters (digital FIR)
Noise Filter	Remark
20 MHz
40 MHz
80 MHz	Available at sample rates ≥200 MS/s.

Table 17. AC-coupling cutoff
AC-coupling cutoff (-3 dB)	16.50 Hz

Note Verified using a 50 Ω source.

Table 18. Rise/fall time
50 Ω	5.15 ns
1 MΩ	5.25 ns

Note 50% FS input pulse.

Figure 6. 50 Ω Full Bandwidth Frequency Response, 1.4 V_pk-pk, Measured

Spectral Characteristics

Note For 1 MΩ, verified using a 50 Ω source and 50 Ω feedthrough terminator.

Table 19. Spurious-Free Dynamic Range (SFDR), 50 Ω and 1 MΩ⁶ -1 dBFS input signal corrected to FS. 358 Hz resolution bandwidth.^[6]
Input Range (V_pk-pk)	Full Bandwidth, Input Frequency ≤30 MHz
0.2 V	-70 dBc
0.7 V	-78 dBc
1.4 V	-71 dBc
5 V	-80 dBc

Table 20. Total Harmonic Distortion (THD), 50 Ω and 1 MΩ^[7]⁷ -1 dBFS input signal corrected to FS. Includes the 2^nd through the 5^th harmonics.
Input Range (V_pk-pk)	Full Bandwidth, Input Frequency ≤30 MHz
0.2 V	-74 dBc
0.7 V	-77 dBc
1.4 V	-70 dBc
5 V	-77 dBc

Table 21. Effective Number of Bits (ENOB), 50 Ω and 1 MΩ^[6]
Input Range (V_pk-pk)	20 MHz Filter Enabled, Input Frequency ≤10 MHz	Full Bandwidth, Input Frequency >10 MHz, ≤30 MHz
0.2 V	9.8	9.5
0.7 V	11.4	10.8
1.4 V	11.9	10.8
5 V	11.8	11.0

Figure 7. 50 Ω Single-Tone Spectrum, 1.4 V_pk-pkInput Range, Full Bandwidth, 9.9 MHz Input Tone at -1 dBFS, Measured

Noise

Note Verified using a 50 Ω terminator connected to input.

Table 22. RMS Noise, 50 Ω and 1 MΩ, Warranted
Input Range (V_pk-pk)	RMS Noise (% of Full Scale)
0.2 V	0.045
All other input ranges	0.018

Figure 8. 50 Ω Average Noise Density, 1.4 V_pk-pk Range, Measured

Figure 9. 50 Ω Average Noise Density, 0.2 V_pk-pk Range, Measured

Skew

Channel-to-channel skew^[8]⁸ For input frequencies <90 MHz.

<120 ps

Horizontal

Sample Clock

Sources

Internal

Onboard clock (internal VCXO)

External

AUX 0 CLK IN (front panel MHDMR connector)

PXIe_DStarA (backplane connector)

Sample rate range, real-time^[9]⁹ Divide by n decimation from 250 MS/s. For more information about the Sample Clock topic in the NI SCOPE User Manual.

3.815 kS/s to 250 MS/s

Sample clock jitter^[10]¹⁰ Integrated from 100 Hz to 10 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter.

700 fs RMS

Timebase frequency

Internal (software-selectable)

250 MHz

200 MHz

150 MHz

External

150 MHz to 250 MHz

Timebase accuracy
Phase-locked to onboard clock	±25 ppm, warranted
Phase-locked to external clock	Equal to the external clock accuracy

DC accuracy sampling drift, ±(% of |Reading|) per MHz from 250 MHz^[11]¹¹ Used to calculate additional DC accuracy error when using a base sample clock that is less than 250 MHz. To calculate the additional error, take the difference of the base sample clock rate from 250 MHz, divide by 1,000,000, and multiply by the DC accuracy sampling drift.

±0.0127

Duty cycle tolerance

45% to 55%

Phase-Locked Loop (PLL) Reference Clock

Sources

Internal

None (internal VCXO)

Onboard clock (internal VCXO)

PXI_Clk10 (backplane connector)

External (10 MHz)^[12]¹² The PLL reference clock must be accurate to ±25 ppm.

AUX 0 CLK IN (front panel MHDMR connector)

Duty cycle tolerance

45% to 55%

External Sample Clock

Source

AUX 0 CLK IN (front panel MHDMR connector)

Impedance

50 Ω

Coupling

Input voltage range
As a 250 MHz sine wave	1 dBm through 18 dBm
As a fast slew rate input (square wave, V_pk-pk)	0.4 V to 5 V

Maximum input overload
As a 250 MHz sine wave	20 dBm
As a fast slew rate input (square wave, V_pk-pk)	6 V

External Reference Clock In

Source

AUX 0 CLK IN (front panel MHDMR connector)

Impedance

50 Ω

Coupling

Frequency^[13]¹³ The PLL reference clock must be accurate to ±25 ppm.

10 MHz

Input voltage range
As a 250 MHz sine wave	1 dBm through 18 dBm
As a fast slew rate input (square wave, V_pk-pk)	6 V

Duty cycle tolerance

45% to 55%

Reference Clock Out

Source	PXI_Clk10 (backplane connector)
Destination	AUX 0 CLK OUT
Output impedance	50 Ω
Logic type	3.3 V LVCMOS
Maximum current drive	±8 mA

PXIe_DStarA

Source	System timing slot
Destinations	Onboard clock (internal VCXO)

PXI_Clk10

Source	PXI backplane
Destination	Reference clock

Trigger

Supported triggers	Reference (stop) trigger Reference (arm) trigger Start trigger Advance trigger
Trigger types	Edge Hysteresis Window Digital Immediate Software
Dead time	Sample clock period × 10
Holdoff	From Dead time to [(2⁶⁴ - 1) × Sample clock period]
Delay	From 0 to [(2⁵¹ - 1) × Sample clock period]

For more information about triggers, refer to Triggering in NI-SCOPE.

Analog Trigger

Sources
PXIe-5108 (4 CH)	CH <0..3>
PXIe-5108 (8 CH)	CH <0..7>

Table 23. Analog Trigger Time Resolution and Rearm Time
Interpolator Status	Time Resolution	Rearm Time
Enabled	Sample clock period / 1024	Sample clock period × 124
Disabled	Sample clock period	Sample clock period × 84

Trigger accuracy¹⁴ For input frequencies <90 MHz.^[14]
Input range (V_pk-pk): 0.2 V	0.75% of FS
Input range (V_pk-pk): 0.7 V, 1.4 V, 5 V	0.5% of FS

Trigger jitter^[14]

15 ps RMS

Minimum threshold duration^[15]¹⁵ Data must exceed each corresponding trigger threshold for at least the minimum duration to ensure analog triggering.

Sample clock period

Digital Trigger

Sources	AUX 0 PFI <0..7> PXI_Trig <0..6>
Time resolution	Sample clock period × 2
Rearm time	Sample clock period × 84
Approximate trigger delay difference between analog edge trigger and digital trigger source^[16]¹⁶ This value is approximate because changes to the digital trigger routing or the analog signal path affect propagation delay. You can compensate for the delay difference by adjusting the NI-SCOPE trigger delay value. Add an additional 80 ns trigger delay when passing a trigger between PXIe-5108 modules. With the same hardware and software configuration, the trigger delay difference is consistent within the timing resolution across modules of the same model. For more information about the trigger delay difference, refer to Characterizing Setup to Account for Delay on Digital Trigger.	630 ns, nominal

Software Trigger

Destinations

Reference (stop) trigger

Reference (arm) trigger

Start trigger

Advance trigger

Time resolution

Sample clock period × 2

Rearm time

Sample clock period × 84

Programmable Function Interface

Connector

AUX 0 PFI <0..7> (front panel MHDMR connector)

Direction

Bidirectional per channel

Direction control latency

125 ns

As an input (trigger)
Destinations	Start trigger (acquisition arm) Reference (stop) trigger Arm Reference trigger Advance trigger
Input impedance	49.9 kΩ
V_IH	2 V
V_IL	0.8 V
Maximum input overload	0 V to 3.3 V (5 V tolerant)
Minimum pulse width	10 ns

As an output (event)
Sources	Ready for Start Start trigger (acquisition arm) Ready for Reference Reference (stop) trigger End of Record Ready for Advance Advance trigger Done (End of Acquisition)
Output impedance	50 Ω
Logic type	3.3 V CMOS
Maximum current drive	12 mA
Minimum pulse width	10 ns

Power Output (+3.3 V)

Connector	AUX 0 +3.3 V (front panel MHDMR connector)
Voltage output	3.3 V ±10%
Maximum current drive	200 mA
Output impedance	<1 Ω

Waveform

Onboard memory size^[17]¹⁷ Onboard memory is shared among all enabled channels.
PXIe-5108 (4 CH)	256 MB
PXIe-5108 (8 CH)	512 MB

Minimum record length

1 sample

Number of pretrigger samples

Zero up to (Record length - 1)

Number of posttrigger samples

Zero up to Record length

Maximum number of records in onboard memory

Total onboard memory / 48 × Number of channels, where number of channels is the number of channels enabled rounded up to the nearest power of two

Figure 10. Allocated Onboard Memory Per Record

Roundup (Roundup (\frac{Coerced number of samples + Number of samples per sample word}{Number of samples per memory word}) \times Number of samples per memory word + 3 \times Number of samples per memory word) \times Bytes per sample \times Number of channels

where

Number of samples per sample word = 16 samples / number of channels
Number of samples per memory word = 48 samples / number of channels
Coerced number of samples is the number of pretrigger samples rounded up to the next multiple of Number of samples per sample word + the number of posttrigger samples rounded up to the next multiple of number of samples per sample word
Number of channels is the number of channels enabled rounded up to the nearest power of two

Memory Sanitization

For information about memory sanitization, refer to the letter of volatility for your device, which is available at ni.com/manuals.

Calibration

External Calibration

External calibration yields the following benefits:

Corrects for gain and offset errors of the onboard references used in self-calibration.
Adjusts timebase accuracy.
Compensates the 1 MΩ ranges.

All calibration constants are stored in nonvolatile memory.

Self-Calibration

Self-calibration is done on software command.

The calibration corrects for the following aspects:

Gain
Offset
Intermodule synchronization errors

Refer to the NI High-Speed Digitizers Help for information about when to self-calibrate the device.

Calibration Specifications

Interval for external calibration	2 years
Warm-up time^[18]¹⁸ Warm-up begins after the chassis and controller or PC is powered, the PXIe-5108 is recognized by the host, and the PXIe-5108 is configured in NI-SCOPE. Self-calibration is recommended following the specified warm-up time.	15 minutes

Software

Driver Software

This device was first supported in NI-SCOPE 2025 Q3. NI-SCOPE provides application programming interfaces for many development environments.

Application Software

NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

LabVIEW
LabWindows™/CVI™
Measurement Studio
Microsoft Visual C/C++
.NET (C# and VB.NET)

TClk Specifications

You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

Intermodule Synchronization Using NI-TClk for Identical Modules

Synchronization specifications are valid under the following conditions:

All modules are installed in one PXI Express chassis.
The NI-TClk driver is used to align the Sample clocks of each module.
All parameters are set to identical values for each SMC-based module.
Modules are synchronized without using an external Sample clock.
Self-calibration is completed.

Note Although you can use NI-TClk to synchronize non-identical modules, these specifications apply only to synchronizing identical modules.

Skew^[19]¹⁹ Caused by clock and analog path delay differences. No manual adjustment performed. Tested with a PXIe-1082 chassis with a maximum slot-to-slot skew of 100 ps. Valid within ±1 °C of self-calibration.	300 ps
Skew after manual adjustment	≤10 ps
Sample clock delay/adjustment resolution	3.5 ps

Power

Table 24. Power Consumption
PXIe-5108 (4 CH) power consumption
+3.3 V DC	6.5 W, typical
+12 V DC	13.75 W, typical
Total power	20.25 W, typical
PXIe-5108 (8 CH) power consumption
+3.3 V DC	8.5 W, typical
+12 V DC	18 W, typical
Total power	26.5 W, typical

Physical

Dimensions

3U, one-slot, PXI Express Gen 2 x8 Module

18.5 cm × 2.0 cm × 13.0 cm

(7.3 in × 0.8 in × 5.1 in)

Weight
PXIe-5108 (4 CH)	449 g (15.8 oz)
PXIe-5108 (8 CH)	461 g (16.3 oz)

Environment


Maximum altitude	2,000 m (800 mbar) (at 25 °C ambient temperature)
Pollution Degree	2

Indoor use only.

Operating Environment

Ambient temperature range	0 °C to 45 °C
Relative humidity range	10% to 90%, noncondensing

Storage Environment


Ambient temperature range, storage	-40 °C to 71 °C
Relative humidity range, storage	5% to 95%, noncondensing

Shock and Vibration


Operating shock	30 g peak, half-sine, 11 ms pulse
Random vibration	Operating: 5 Hz to 500 Hz, 0.3 g RMS Nonoperating: 5 Hz to 500 Hz, 2.4 g RMS

Compliance and Certifications

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

IEC 61010-1, EN 61010-1
UL 61010-1, CSA C22.2 No. 61010-1

Note For safety certifications, refer to the product label or the Product Certifications and Declarations section.

¹ Warm-up begins after the chassis and controller or PC is powered, the PXIe-5108 is recognized by the host, and the PXIe-5108 is configured in NI-SCOPE. Self-calibration is recommended following the specified warm-up time.

² For more information about cooling, refer to your chassis documentation and the Maintain Forced-Air Cooling Note to Users.

³ Mini-HDMI and MHDMR are equivalent connectors.

⁴ Derated to 5 V_pk-pk for periodic waveforms with frequencies below 100 kHz.

⁵ Verified using a 50 Ω source and 50 Ω feedthrough terminator.

⁶ -1 dBFS input signal corrected to FS. 358 Hz resolution bandwidth.

⁷ -1 dBFS input signal corrected to FS. Includes the 2^nd through the 5^th harmonics.

⁸ For input frequencies <90 MHz.

⁹ Divide by n decimation from 250 MS/s. For more information about the Sample Clock topic in the NI SCOPE User Manual.

¹⁰ Integrated from 100 Hz to 10 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter.

¹¹ Used to calculate additional DC accuracy error when using a base sample clock that is less than 250 MHz. To calculate the additional error, take the difference of the base sample clock rate from 250 MHz, divide by 1,000,000, and multiply by the DC accuracy sampling drift.

¹² The PLL reference clock must be accurate to ±25 ppm.

¹³ The PLL reference clock must be accurate to ±25 ppm.

¹⁴ For input frequencies <90 MHz.

¹⁵ Data must exceed each corresponding trigger threshold for at least the minimum duration to ensure analog triggering.

¹⁶ This value is approximate because changes to the digital trigger routing or the analog signal path affect propagation delay. You can compensate for the delay difference by adjusting the NI-SCOPE trigger delay value. Add an additional 80 ns trigger delay when passing a trigger between PXIe-5108 modules. With the same hardware and software configuration, the trigger delay difference is consistent within the timing resolution across modules of the same model. For more information about the trigger delay difference, refer to Characterizing Setup to Account for Delay on Digital Trigger.

¹⁷ Onboard memory is shared among all enabled channels.

¹⁸ Warm-up begins after the chassis and controller or PC is powered, the PXIe-5108 is recognized by the host, and the PXIe-5108 is configured in NI-SCOPE. Self-calibration is recommended following the specified warm-up time.

¹⁹ Caused by clock and analog path delay differences. No manual adjustment performed. Tested with a PXIe-1082 chassis with a maximum slot-to-slot skew of 100 ps. Valid within ±1 °C of self-calibration.