Specifies the Sample Clock source.

Note The signal generator must not be in the Generating state when you change this property. To change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete.

Remarks

The following table lists the characteristics of this property.

Short Name Sample Clock Source
Data type cstr.png
Permissions Read/Write
High-level VIs niFgen Configure Sample Clock Source
Channel-based No
Resettable Yes
Onboard Clock OnboardClock

Specifies that the onboard clock is used as the Sample Clock source.
Clock In ClkIn

Specifies that the signal at the CLK IN front panel connector is used as the Sample Clock source.
PXI STAR Line PXI_Star

Specifies that the PXI_STAR trigger line is used as the Sample Clock source.
PXI Trigger Line 0/RTSI 0 PXI_Trig0

Specifies that the PXI or RTSI line 0 is used as the Sample Clock source.
PXI Trigger Line 1/RTSI 1 PXI_Trig1

Specifies that the PXI or RTSI line 1 is used as the Sample Clock source.
PXI Trigger Line 2/RTSI 2 PXI_Trig2

Specifies that the PXI or RTSI line 2 is used as the Sample Clock source.
PXI Trigger Line 3/RTSI 3 PXI_Trig3

Specifies that the PXI or RTSI line 3 is used as the Sample Clock source.
PXI Trigger Line 4/RTSI 4 PXI_Trig4

Specifies that the PXI or RTSI line 4 is used as the Sample Clock source.
PXI Trigger Line 5/RTSI 5 PXI_Trig5

Specifies that the PXI or RTSI line 5 is used as the Sample Clock source.
PXI Trigger Line 6/RTSI 6 PXI_Trig6

Specifies that the PXI or RTSI line 6 is used as the Sample Clock source.
PXI Trigger Line 7/RTSI 7 PXI_Trig7

Specifies that the PXI or RTSI line 7 is used as the Sample Clock source.
DDC Clock In DDC_ClkIn

Specifies that the Sample Clock from DDC connector is used as the Sample Clock source.