Filters for Counter and Timer Signals
- Updated2025-08-09
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Filters for Counter and Timer Signals
You can enable programmable debouncing filters on each DIO <0..15> signal. These filters are available when you use a DIO <0..15> signal as a counter, timer, or trigger signal.
When the filters are enabled, USB-6453 samples the input on each rising edge of a filter clock. The USB-6453 uses an onboard oscillator to generate the filter clock.
The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the filter clock samples the signal high on N consecutive edges, the low-to-high transition propagates to the rest of the circuit. The value of N depends on the filter setting as illustrated in the following table.
| Filter Setting | Filter Clock | N (Filter Clocks Needed to Pass Signal) | Pulse Width Guaranteed to Pass Filter | Pulse Width Guaranteed to Not Pass Filter |
|---|---|---|---|---|
| None | — | — | — | — |
| 90 ns (short) | 100 MHz | 9 | 90 ns | 80 ns |
| 5.12 µs (medium) | 100 MHz | 512 | 5.12 µs | 5.11 µs |
| 2.56 ms (high) | 100 kHz | 256 | 2.56 ms | 2.55 ms |
| Custom | User configurable | N | N/timebase | (N - 1)/ timebase |
The filter setting for each input can be configured independently. On power up, the filters are disabled. The following figure shows an example of a low to high transition on an input that has a custom filter set to N = 5.
Enabling filters introduces jitter on the input signal. The maximum jitter is one period of the timebase.