Digital Input Timing Signals

You can specify an internal or external source for DI Sample Clock. You can also specify whether the measurement sample begins on the rising edge or falling edge of DI Sample Clock.

If the USB-6421 receives a DI Sample Clock when the FIFO is full, it reports an overflow error to the host software.

Using an Internal Source

To use DI Sample Clock with an internal source, specify the signal source and the polarity of the signal. The source can be any of the following signals:

• DI Sample Clock (di/SampleClock)
• DO Sample Clock (do/SampleClock)
• AI Sample Clock (ai/SampleClock)
• AI Convert Clock (ai/ConvertClock)
• AO Sample Clock (ao/SampleClock)
• Counter n Sample Clock
• Counter n Internal Output
• Frequency Output
• DI Change Detection output

Several other internal signals can be routed to DI Sample Clock through internal routes. Refer to Device Routing in MAX for more information.

Using an External Source

You can route any DIO <0..15> signals as DI Sample Clock. You can sample data on the rising or falling edge of DI Sample Clock.

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock out to any DIO <0..15> terminal. The DIO circuitry inverts the polarity of DI Sample Clock before driving the DIO terminal.

Other Timing Requirements

The USB-6421 only acquires data during an acquisition. It ignores DI Sample Clock when a measurement acquisition is not in progress. During a measurement acquisition, you can cause the USB-6421 to ignore DI Sample Clock using the DI Pause Trigger signal.

The DI timing engine on the USB-6421 internally generates DI Sample Clock unless you select an external source. DI Start Trigger starts the timing engine and either software or hardware can stop it once a finite acquisition completes. When using the DI timing engine, you can also specify a configurable delay from DI Start Trigger to the first DI Sample Clock pulse.

By default, this delay is set to two ticks of the DI Sample Clock Timebase signal.

• 100 MHz Timebase (default)
• 20 MHz Timebase
• 100 kHz Timebase
• DIO <0..15>

Refer to the device routing table in MAX for all additional routable signals. To find the device routing table for your device, launch MAX and select Devices and Interfaces » NI-DAQmx Devices. Click a device to open a tabbed window in the middle pane. Click the Device Routes tab at the bottom of the pane to display the device routing table.

DI Sample Clock Timebase is not available as an output on the I/O connector. DI Sample Clock Timebase is divided down to provide one of the possible sources for DI Sample Clock. You can configure the polarity selection for DI Sample Clock Timebase as either rising or falling edge except for the 100 MHz Timebase or 20 MHz Timebase.

You might use DI Sample Clock Timebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal, but do not need to divide the signal, then you should use DI Sample Clock rather than DI Sample Clock Timebase.

A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. Once the acquisition begins, configure the acquisition to stop:

• When a certain number of points are sampled (in finite mode)
• After a hardware reference trigger (in finite mode)
• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a post-triggered acquisition.

Retriggerable DI

The DI Start Trigger is configurable as retriggerable. When the DI Start Trigger is configured as retriggerable, the timing engine generates the sample and convert clocks for the configured acquisition in response to each pulse on a DI Start Trigger signal.

The timing engine ignores the DI Start Trigger signal while the clock generation is in progress. After the clock generation is finished, the timing engine waits for another Start Trigger to begin another clock generation. The following figure shows a retriggerable DI of four samples.

Reference triggers are not retriggerable.

Using a Digital Source

To use DI Start Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• DIO <0..15>
• Counter n Internal Output
• Change Detection Event
• AI Start Trigger (ai/StartTrigger)
• AO Start Trigger (ao/StartTrigger)
• DO Start Trigger (do/StartTrigger)

The source can also be one of several other internal signals on the USB-6421. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition begins on the rising edge or falling edge of DI Start Trigger.

Routing DI Start Trigger to an Output Terminal

You can route DI Start Trigger out to any DIO <0..15> terminal. The output is an active high pulse. All digital I/O terminals are configured as inputs by default.

The USB-6421 also uses DI Start Trigger to initiate pre-triggered DAQ operations. In most pre-triggered applications, a software trigger generates DI Start Trigger. Refer to the DI Reference Trigger Signal section for a complete description of the use of DI Start Trigger and DI Reference Trigger in a pre-triggered DAQ operation.

To use a reference trigger, specify a buffer of finite size and a number of pre-trigger samples (samples that occur before the reference trigger). The number of post-trigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pre-trigger samples.

Once the acquisition begins, the USB-6421 writes samples to the buffer. After the USB-6421 captures the specified number of pre-trigger samples, it begins to look for the reference trigger condition. If the reference trigger condition occurs before the USB-6421 captures the specified number of pre-trigger samples, the USB-6421 ignores the condition.

If the buffer becomes full, the USB-6421 continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the USB-6421 discards it. Refer to the document Can a Pretriggered Analog Acquisition be Continuous? for more information.

When the reference trigger occurs, the USB-6421 continues to write samples to the buffer until the buffer contains the number of post-trigger samples desired. The following figure shows the final buffer.

Using a Digital Source

To use DI Reference Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• DIO <0..15>
• Change Detection Event
• Counter n Internal Output
• AI Reference Trigger (ai/ReferenceTrigger)
• AO Start Trigger (ao/StartTrigger)
• DO Start Trigger (do/StartTrigger)

The source can also be one of several internal signals on the USB-6421. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition stops on the rising or falling edge or falling edge of DI Reference Trigger.

Routing DI Reference Trigger Signal to an Output Terminal

You can route DI Reference Trigger out to any DIO <0..15> terminal.

The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low, as shown in the following figure. In the figure, T represents the period, and A represents the unknown time between the clock pulse and the post-trigger.

Using a Digital Source

To use DI Pause Trigger, specify a source and a polarity. The source can be any of the following signals:

• DIO <0..15>
• Counter n Internal Output
• Counter n Gate
• AI Pause Trigger (ai/PauseTrigger)
• AO Pause Trigger (ao/PauseTrigger)
• DO Pause Trigger (do/PauseTrigger)

The source can also be one of several other internal signals on the USB-6421. Refer to Device Routing in MAX for more information.

Routing DI Pause Trigger Signal to an Output Terminal

You can route DI Pause Trigger out to any DIO <0..15> terminal.