Analog Input Timing Signals

The USB-6421 samples the AI signals of every channel in the task once for every AI Sample Clock. A measurement acquisition consists of one or more samples.

You can specify an internal or external source for AI Sample Clock. You can also specify whether the measurement sample begins on the rising edge or falling edge of AI Sample Clock.

Using an Internal Source

One of the following internal signals can drive AI Sample Clock:

• Counter n Internal Output
• AI Sample Clock Timebase (divided down)
• A pulse initiated by host software
• Change Detection Event
• Counter n Sample Clock
• AO Sample Clock (ao/SampleClock)
• DI Sample Clock (di/SampleClock)
• DO Sample Clock (do/SampleClock)

A programmable internal counter divides down the sample clock timebase.

Several other internal signals can be routed to AI Sample Clock through internal routes.

Using an External Source

Use DIO <0..15> as the source of AI Sample Clock.

Routing AI Sample Clock Signal to an Output Terminal

You can route AI Sample Clock out to any DIO <0..15> terminal. This pulse is always active high.

Other Timing Requirements

The USB-6421 only acquires data during an acquisition. It ignores AI Sample Clock when a measurement acquisition is not in progress. During a measurement acquisition, you can cause the USB-6421 to ignore AI Sample Clock using the AI Pause Trigger signal.

A counter/timing engine on the USB-6421 internally generates AI Sample Clock unless you select some external source. AI Start Trigger starts this counter and either software or hardware can stop it once a finite acquisition completes. When using the AI timing engine, you can also specify a configurable delay from AI Start Trigger to the first AI Sample Clock pulse. By default, this delay is set to four ticks of the AI Sample Clock Timebase signal.

When using an externally generated AI Sample Clock, you must ensure the clock signal is consistent with respect to the timing requirements of AI Convert Clock. Failure to do so may result in a scan overrun and will cause an error. Refer to the AI Convert Clock Signal section for more information about the timing requirements between AI Convert Clock and AI Sample Clock. The following figure shows the relationship of AI Sample Clock to AI Start Trigger.

You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal:

• 100 MHz Timebase (default)
• 20 MHz Timebase
• 100 kHz Timebase
• DIO <0..15>

AI Sample Clock Timebase is not available as an output on the I/O connector. AI Sample Clock Timebase is divided down to provide one of the possible sources for AI Sample Clock. You can configure the polarity selection for AI Sample Clock Timebase as either rising or falling edge, except on 100 MHz Timebase or 20 MHz Timebase.

A sample (controlled by the AI Sample Clock) consists of one or more conversions. You can specify either an internal or external signal as the source of AI Convert Clock. You can also specify whether the measurement sample begins on the rising edge or falling edge of 
AI Convert Clock.

With NI-DAQmx, the driver chooses the fastest conversion rate possible based on the speed of the A/D converter and adds 10 μs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time. If the AI Sample Clock rate is too fast to allow for this 10 μs of padding, NI-DAQmx chooses the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample.

To explicitly specify the conversion rate, use AI Convert Clock Rate DAQmx Timing property node or function.

Using an Internal Source

One of the following internal signals can drive AI Convert Clock:

• AI Convert Clock Timebase (divided down)
• Counter n Internal Output
• Change Detection Event
• Counter n Sample Clock
• AO Sample Clock (ao/SampleClock)
• DI Sample Clock (di/SampleClock)
• DO Sample Clock (do/SampleClock)

A programmable internal counter divides down the AI Convert Clock Timebase to generate AI Convert Clock. The counter is started by AI Sample Clock and continues to count down to zero, produces an AI Convert Clock, reloads itself, and repeats the process until the sample is finished. It then reloads itself in preparation for the next AI Sample Clock pulse.

Several other internal signals can be routed to AI Convert Clock through internal routes. Refer to Device Routing in MAX for more information.

Using an External Source

Use DIO <0..15> as the source of AI Convert Clock.

Routing AI Convert Clock Signal to an Output Terminal

You can route AI Convert Clock (as an active low signal) out to any DIO <0..15> terminal.

Using a Delay from Sample Clock to Convert Clock

When using the AI timing engine to generate your Convert Clock, you can also specify a configurable delay from AI Sample Clock to the first AI Convert Clock pulse within the sample. By default, this delay is three ticks of AI Convert Clock Timebase. The following figure shows the relationship of AI Sample Clock to AI Convert Clock.

Other Timing Requirements

Some clock signals are gated off unless the proper timing requirements are met because of how the sample and conversion level timing of the USB-6421 work.

For example, the USB-6421 ignores both AI Sample Clock and AI Convert Clock until it receives a valid AI Start Trigger signal. Similarly, it ignores all AI Convert Clock pulses until it recognizes an AI Sample Clock pulse. Once the USB-6421 receives the correct number of AI Convert Clock pulses, it ignores subsequent AI Convert Clock pulses until it receives another AI Sample Clock. However, after the USB-6421 recognizes an AI Sample Clock pulse, it causes an error if it receives an AI Sample Clock pulse before the correct number of AI Convert Clock pulses are received.

The following figures show timing sequences for a four-channel acquisition (using AI channels 0, 1, 2, and 3) and demonstrate proper and improper sequencing of AI Sample Clock and AI Convert Clock.

The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is divided down to provide one of the possible sources for AI Convert Clock. Use one of the following signals as the source of AI Convert Clock Timebase:

• AI Sample Clock Timebase
• 100 MHz Timebase

AI Convert Clock Timebase is not available as an output on the I/O connector.

You can route AI Hold Complete Event out to any DIO <0..15>.

The polarity of AI Hold Complete Event is software-selectable, but it is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.

A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. Once the acquisition begins, configure the acquisition to stop:

• When a certain number of points are sampled (in finite mode)
• After a hardware reference trigger (in finite mode)
• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a post-triggered acquisition.

Retriggerable Analog Input

The AI Start Trigger is configurable as retriggerable. The timing engine generates the sample and convert clocks for the configured acquisition in response to each pulse on an AI Start Trigger signal.

The timing engine ignores the AI Start Trigger signal while the clock generation is in progress. After the clock generation is finished, the counter waits for another Start Trigger to begin another clock generation. The following figure shows a retriggerable analog input with three AI channels and four samples per trigger.

Reference triggers are not retriggerable.

Using a Digital Source

To use AI Start Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• DIO <0..15>
• Counter n Internal Output
• Change Detection Event
• AO Start Trigger (ao/StartTrigger)
• DI Start Trigger (di/StartTrigger)
• DO Start Trigger (do/StartTrigger)

The source can also be one of several other internal signals on the USB-6421. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition begins on the rising edge or falling edge of AI Start Trigger.

Routing AI Start Trigger to an Output Terminal

You can route AI Start Trigger out to any DIO <0..15> terminal. The output is an active high pulse.

The USB-6421 also uses AI Start Trigger to initiate pre-triggered DAQ operations. In most pre-triggered applications, a software trigger generates AI Start Trigger.

Refer to the AI Reference Trigger Signal section for a complete description of the use of AI Start Trigger and AI Reference Trigger in a pre-triggered DAQ operation.

To use a reference trigger, specify a buffer of finite size and a number of pre-trigger samples (samples that occur before the reference trigger). The number of post-trigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pre-trigger samples.

Once the acquisition begins, the USB-6421 writes samples to the buffer. After USB-6421 captures the specified number of pre-trigger samples, it begins to look for the reference trigger condition. If the reference trigger condition occurs before the USB-6421 captures the specified number of pre-trigger samples, it ignores the condition.

If the buffer becomes full, the USB-6421 continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the USB-6421 discards it. Refer to Can a Pre-triggered Analog Acquisition be Continuous? for more information.

When the reference trigger occurs, the USB-6421 continues to write samples to the buffer until the buffer contains the number of post-trigger samples desired. The following figure shows the final buffer.

Using a Digital Source

To use AI Reference Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• DIO <0..15>
• Change Detection Event
• Counter n Internal Output
• DI Reference Trigger (di/ReferenceTrigger)
• DO Start Trigger (do/StartTrigger)
• AO Start Trigger (ao/StartTrigger)

The source can also be one of several internal signals on the USB-6421. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition stops on the rising edge or falling edge of AI Reference Trigger.

Routing AI Reference Trigger Signal to an Output Terminal

You can route AI Reference Trigger out to any DIO <0..15> terminal.

The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low, as shown in the following figure. In the figure, T represents the period, and A represents the unknown time between the clock pulse and the post-trigger.

Using a Digital Source

To use AI Pause Trigger, specify a source and a polarity. The source can be one of the following signals:

• DIO <0..15>
• Counter n Internal Output
• Counter n Gate
• AO Pause Trigger (ao/PauseTrigger)
• DO Pause Trigger (do/PauseTrigger)
• DI Pause Trigger (di/PauseTrigger)

The source can also be one of several other internal signals on your USB-6421. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition stops on the rising edge or falling edge of AI Reference Trigger.

Routing AI Pause Trigger Signal to an Output Terminal

You can route AI Pause Trigger out to any DIO <0..15> terminal.