Digital Input and Output

The IoPort.vhd file allows the implementation of bi-directional signals on the CPLD. The entity is configurable via generics to set its address base and its port size. Each instantiated block will add three registers of the same size that are defined by the generic kPortSize. Because of this, if the entity is instantiated, you should avoid adding other registers in the range kAddress to kAddress + 2 where kAddress is the address generic of the entity.

The maximum length of kPortSize is 64.

Table 4. Register Descriptions
Register Name Address Type Explanation
Output kAddress R/W The value of this register defines the output state when the corresponding direction bit is set as output (1).
Direction kAddress + 1 R/W For each pin of the port, 1 configures the pin as an output and 0 configures the pin an input.
Input kAddress + 2 R Mirrors the state of the external pin for read.
Table 5. Signal Descriptions
Signal Name Direction Explanation
Generics
kAddress N/A Defines the base address of the block. This address will also correspond to the Output register. The next two consecutive addresses are assigned to Direction and Input.
kPortSize N/A Determines the number of I/O implemented. Acceptable values go from 1 to 64.
Signals
aReset In Board Reset Signal
Clk In Stable clock provided by the CPLD.
caIoPort In/Out Digital input/output.
cRegPortOut Out Signals to the EdBlock Register Port.
cRegPortIn In Signals from the EdBlock Register Port.