SYS_RST#

The SYS_RST# signal is a system reset signal for resetting the sbRIO-96xx processor and FPGA. Asserting this signal causes the RMC RST# signal to also assert. The SYS_RST# signal asserts low. SYS_RST# is pulled to 3.3 V with a 4.75 kΩ resistor when in Run Mode, Safe Mode, and Sleep Mode.

The amount of time for which you assert this signal determines the specific reset behavior.

You can assert the SYS_RST# signal before you apply power to the sbRIO-96xx. The sbRIO-96xx remains in reset until the SYS_RST# signal de-asserts. If you assert the SYS_RST# signal before power is applied, then you must de-assert the SYS_RST# signal within five seconds.

Sleep Mode is an advanced feature. You can use the Linux “shutdown -h now” command to send the system into Sleep Mode. You can wake up the system by asserting SYS_RST# low.