The Aurora links between the RTG VST and the Coprocessor do not natively provide a deterministic latency for data, which could lead to errors in expected delay settings from Coprocessor supplied signals. To address this behavior, a buffering and initialization scheme has been added to the VST’s implementation of Aurora. This requires informing the VST of what the desired round-trip latency is for data that enters the VST Rx port, is passed to the Coprocessor, is passed back to the VST, and is then generated on the VST Tx port.

The buffering for this technique has limits. Specifying a minimum latency that is too low will cause the buffers to underflow. Specifying a minimum latency that is too high will cause the buffers to overflow. Call the Coprocessor Link Status function to determine if there are underflows or overflows.

The value of this round-trip latency depends on the algorithm in the Coprocessor. For example, the template is a simple loopback where input is directly connected to output with no additional processing clocks. Refer to the minimum latency settings in the following table. The RTG clock resolution is 6.4 ns. For every feedback node the custom algorithm requires the data to pass-thru will add more latency. Find the number of clocks it takes output valid from the read function to make it to input valid on the write function. Each clock would add 6.4 ns to the minimum latency.

Table 38. RTG/Coprocessor Characteristics
RTG Coprocessor Sample Rate for Baseband Data Approximate Minimum Latency
PXIe-5830/5831/5832/5841 PXIe-6594 1.25 GS/s ~2.7 µs
PXIe-5830/5831/5832/5841 PXIe-7903 1.25 GS/s ~2.7 µs
PXIe-5842 PXIe-7903 2.50 GS/s ~5.2 µs