The RTG uses the Instruction Framework (IFW) Instrument Design Library (IDL). The IFW provides a way to create reusable FPGA modules that provide host communication. It requires a set of VIs and controls/indicators on the top level VI. These are provided in the template VI and can be copied as needed.

It is not required, however NI recommends that you create custom modules that use the IFW. You must add any created custom module to the IFW bus by adding additional calls of the Add Subsystems VI from the Register Configuration class library.

Instruction Framework Overview

Use the Instruction Framework instrument design library to build a communication network in LabVIEW FPGA. The network has two types of endpoints: Instruction Producers and Address Spaces. Instruction Producers issue read and write instructions that are targeted for a particular Address Space. When the destination Address Space completes an instruction, it provides a response which is routed back to the Instruction Producer that issued the instruction, as shown in the following diagram:

The Instruction Framework instrument design library includes some host VIs, to help with communication between host libraries, and FPGA address spaces. The Subsystem Map class provides a way to look-up the location of an Address Space on the host, using the Address Space's unique identifier (UID). A context object is returned from this lookup function, which can be used to specify the destination for a read or write operation.

The Instruction Target class is intended to be used as an abstract interface for the mechanism used to communicate with the Instruction Framework FPGA Network. The FIFO Register Bus instrument design library provides an Instruction Target implementation on the host, which is coupled to an Instruction Producer implementation on the FPGA. This allows a host controller to send instructions to Address Spaces on the FPGA, and read the resulting responses. The instructions are sent to the FPGA using a uniquely named DMA FIFO, and the responses are received using a uniquely named indicator.

Some instrument design libraries use the Instruction Framework as a configuration mechanism. These libraries require a Subsystem Map object to look-up the location of corresponding Address Spaces on the FPGA. These libraries will also require an Instruction Target to provide the communication mechanism from the host controller to an Instruction Producer on the Instruction Framework FPGA Network. The corresponding Address Spaces must be added to the Instruction Framework FPGA Network in order for the host library to communicate properly with the FPGA library. This Address Space implementation provides register access through an Instruction Producer, such as the FIFO Register Bus library, instead of using controls and indicators on the top level of the FPGA diagram.