Specifies the delay, in seconds, to apply to the I/Q waveform.

Relative delay allows for delaying the generated signal from one device relative to the generated signal of another device after those devices have been synchronized. You can achieve a negative relative delay by delaying both synchronized devices by the same value (1 us) before generation begins and then changing the relative delay to a smaller amount than the initial value on only one of the devices.

Note To obtain a negative relative delay when synchronizing the PXIe-5840/5841/5842 with a module that does not support this property, use the NI-TClk Sample Clock Delay property.

To set this property, the NI-RFSG device must be in the Configuration or Generation state.

Note The resolution of this property is a function of the I/Q sample period at 15E(-6) of the sample period but not worse than one Sample Clock period.

Supported Devices: PXIe-5820/5830/5831/5832/5840/5841/5842

Valid Values:

PXIe-5820/5830/5831/5832/5840/5841: 0 us to 3.2 us

PXIe-5842: 0 us to 6.5 us

Related Topics

NI-TClk Overview

Remarks

The following table lists the characteristics of this property.

Short Name Relative Delay
Data type cdbl.png
Permissions Read/Write
High-level VIs N/A
Channel-based No
Resettable Yes