FPGA I/O Node Reference and Programming Notes

Notice When programming XC communication, always plug a cable into Lane 0 before you plug into Lane 1, 2, or 3. Lanes 1, 2, and 3 depend on Lane 0 to communicate, and the use of Lane 1, 2, or 3 without Lane 0 may result in data corruption.
Tip Use the Lane x Error signal listed below to monitor for communication errors in the connections at Lanes 0, 1, 2, and 3.
Note
  • You must choose calibrated analog input and analog output or raw analog input and analog output; they cannot be used simultaneously.
  • You must choose the Quadrature Encoder digital output or the Hall Effect digital output; they cannot be used simultaneously.
Table 6. FPGA I/O Node Signal Names and Descriptions
Signal Name Data Type Direction Clock Domain Signal Description
Motor Clock 100 MHz N/A From Socketed CLIP 100 MHz 100 MHz motor clock signal derived from PXIe 100 MHz clock for analog input, analog output, quadrature encoder digital output and Hall effect digital output.
Conn x AI y Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x AI y Start.
Conn x AI y Start Boolean To Socketed CLIP Motor Clock

Assert high for one clock cycle to start analog input data conversion.
Conn x AI y Valid Boolean From Socketed CLIP Motor Clock Assert high for one clock cycle to read new analog input data.
Conn x AI y Data FXP From Socketed CLIP Motor Clock Returns a fixed-point data range <-10..+10>.
Conn x Raw AI y Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x Raw AI y Start.
Conn x Raw AI y Start Boolean To Socketed CLIP Motor Clock

Assert high for one clock cycle to start raw analog input data conversion.

Conn x Raw AI y Valid Boolean From Socketed CLIP Motor Clock

Assert high for one clock cycle to read new analog input data.
Conn x Raw AI y Data I 16 From Socketed CLIP Motor Clock Two's complement I16 raw data for analog input.
Conn x AO y Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x AO y Valid.
Conn x AO y Valid Boolean To Socketed CLIP Motor Clock Assert high for one clock cycle to write new analog output data.
Conn x AO y Data FXP To Socketed CLIP Motor Clock Sends a fixed-point data range <-10..+10> to analog output.
Conn x Raw AO y Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x Raw AO y Valid .
Conn x Raw AO y Valid Boolean To Socketed CLIP Motor Clock Assert high for one clock cycle to write new analog output raw data.
Conn x Raw AO y Data I 16 To Socketed CLIP Motor Clock Two's complement I 16 raw data for analog output.
Conn x Encoder Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x Encoder Valid .
Conn x Encoder Valid Boolean To Socketed CLIP Motor Clock Assert high for one clock cycle to write new quadrature encoder data.
Conn x Encoder A/B/Z Boolean To Socketed CLIP Motor Clock Writes boolean data for quadrature encoder. You must update A/B/Z encoder data when asserting this signal.
Conn x Hall Ready Boolean From Socketed CLIP Motor Clock This signal must indicate ready high before you assert Conn x Hall Valid .
Conn x Hall Valid Boolean To Socketed CLIP Motor Clock Assert high for one clock cycle to write new Hall effect data.
Conn x Hall 1/2/3 Boolean To Socketed CLIP Motor Clock Writes boolean data for Hall effect. You must update 1/2/3 Hall data when asserting this signal.
Conn x AI y LSB Weight I 32 From Socketed CLIP Motor Clock Returns I 32 data for the calibration LSB weight.
Conn x AI y Offset I 32 From Socketed CLIP Motor Clock Returns I 32 data for the calibration offset.
Conn x AO y LSB Weight I 32 From Socketed CLIP Motor Clock Returns I 32 data for the calibration LSB weight.
Conn x AO y Offset I 32 From Socketed CLIP Motor Clock Returns I 32 data for the calibration offset.
IO Ready Boolean From Socketed CLIP N/A Indicates successful configuration of the I/O module using the default configuration.
IO Error I 32 From Socketed CLIP N/A Returns I/O module errors.
XC Clock 62.5 MHz N/A From Socketed CLIP XC Clock 62.5 MHz derived from I/O module 125 MHz oscillator for XC communication.
Lane x Clear Error Boolean To Socketed CLIP XC Clock Assert on one clock cycle to clear the Lane x Error.
Lane x Ready Boolean From Socketed CLIP XC Clock Lane x Ready high indicates that an Aurora connection is established on this lane, and the lane is ready to transfer XC data.
Lane x Error I 32 From Socketed CLIP XC Clock

Returns error code from data communication.

Bit 0: Aurora Hard Error

Bit 1: Aurora Soft Error

Bit 2: Aurora Frame Error

Bit 3: Reserved (0)

Bit 4: Tx FIFO Overflow Error

Bit 5: Tx FIFO Underflow Error

Bit 6: Rx FIFO Overflow Error

Bit 7: Rx FIFO Underflow Error

Bit [31:8]: Reserved (0)

Lane x POF y Tx Index U 32 To Socketed CLIP XC Clock

Writes Tx Index from XC stream.

Bit 0: POF index valid

Bit 1: Reserved (0)

Bit [31:2]: POF index [31:2]

Lane x POF y Tx Data U 8 To Socketed CLIP XC Clock Writes Tx Data from XC stream.

Bit [3:0]: POF data

Bit 4: POF data valid

Bit 5: POF is null

Bit [7:6]: Reserved (0)
Lane x POF y Rx Index U 32 From Socketed CLIP XC Clock

Returns Rx Index from XC stream.

Bit 0: POF index valid

Bit 1: Reserved (0)

Bit [31:2]: POF index [31:2]

Lane x POF y Rx Data U 8 From Socketed CLIP XC Clock

Returns Rx Data from XC stream.

Bit [3:0]: POF data

Bit 4: POF data valid

Bit 5: POF is null

Bit [7:6]: Reserved (0)