Digital Waveform Acquisition and Input Triggering

You can acquire digital waveforms on the Port 0 DIO lines. The DI waveform acquisition FIFO stores the digital samples. PCIe-6357 and PXIe-6357 devices have a DMA controller dedicated to moving data from the DI waveform acquisition FIFO to system memory. The DAQ device samples the DIO lines on each rising or falling edge of a clock signal (DI Sample Clock).

The following figure summarizes the timing options that the digital input timing engine provides.

Figure 31. Digital Input Timing Options


You can configure each DIO line to be an output, a static input, or a digital waveform acquisition input.

PCIe-6357 and PXIe-6357 devices feature the following digital input timing signals. Signals with an * support digital filtering.

  • DI Sample Clock Signal*
  • DI Sample Clock Timebase Signal
  • DI Start Trigger Signal*
  • DI Reference Trigger Signal*
  • DI Pause Trigger Signal*