SRAM Properties Dialog Box

Right-click the SRAM Bank item in the Project Explorer window and select Properties from the shortcut menu to display this dialog box. Check the Enable SRAM checkbox if it is not already selected to display the following pages in the Category list:

  • General
  • Clock Selections

General Page

Use the General page to configure the type of memory interface that should be used when communicating with external SRAM.

To display this page, in the SRAM Properties dialog box, select General from the Category list.

This page contains the following components:

  • Enable SRAM —Enables the SRAM. Unchecking this box disables access to the SRAM.
  • Memory Interface—Lists all memory interfaces that are compatible with the SRAM. If multiple versions of a memory interface are available, the version information displays next to the memory interface name.
  • Details—Displays general information about the SRAM memory interface.
  • Path—Displays the file system path to the XML file for the currently selected memory interface file.
  • Reload—Reloads the currently selected memory interface in the table. Use the Reload button if you modify a memory interface XML file on disk after you configure it for use with your FPGA target. Reload updates the I/O in the LabVIEW project and details information, but changes may not be visible in the Memory Interface or Path dialog boxes.

    • The PXIe-5645 ships with one memory interface support option, which provides access to the external SRAM memory.

    Clock Selections Page

    Use the Clock Selections page to link each clock port defined by the component-level IP (CLIP) to a clock on the FPGA target. You must add the FPGA clock to the LabVIEW project before you can link to the FPGA clock.

    To display this page, in the SRAM Properties dialog box, select Clock Selections from the Category list.

    This page includes the following components:

  • Component-Level IP Clock—Lists clock(s) defined in the CLIP declaration XML file.
  • Connection—Lists clocks available on the FPGA target.