Sampled Reference Clock
- Updated2023-03-22
- 1 minute(s) read
Sampled Reference Clock
The Sampled Reference Clock is a synchronization signal that exists inside the FPGA when the module is configured to use a 10 MHz external Reference Clock (from either REF IN or PXI_CLK10).
The Sampled Reference Clock is in the Sample Clock domain and asserts for one cycle out of every twelve, corresponding to the rising edge of the 10 MHz Reference Clock.
Note The PXIe-5645 does not support synchronization using daisy-chained Reference Clocks, for example, REF OUT to REF IN. For multidevice synchronization, lock all devices to phase-aligned Reference Clocks.
