The Sample Clock runs at 120 MHz and is exported by the phase-locked loop (PLL).

You can select one of the following resources as the reference signal for the PLL:

  • The internal temperature compensated crystal oscillator (TCXO)
  • The PXIe-5644 REF IN front panel connector
  • PXI_CLK10

The Sample Clock, in turn, is the reference signal for the RF IN and RF OUT internal LO circuits. While the Sample Clock frequency is fixed at 120 MHz, you can achieve high-resolution I/Q data rates using the Fractional Interpolator and Fractional Decimator DSP FPGA VIs.


1378