Before using the NI-5640R Asynchronous Programming palette, complete all the steps in the Using the ni5640R Template section.
  1. Double-click the My Simple Spectrum Analyzer(FPGA).vi to open the VI and then open the block diagram.
  2. Scroll down the block diagram to the area labeled "ADD YOUR CODE HERE."
  3. Place the ADC node on the block diagram in this area.
    The ADC node is located on the Functions palette under Instruments » NI-5640R Asynchronous Programming.
  4. Create a While Loop below the ADC node. The While Loop is located on the Functions palette under Programming » Structures » Timed Structures.
  5. Wire a FALSE constant to the Loop Condition terminal.
  6. Open the front panel of the My Simple Spectrum Analyzer (FPGA) VI and create a Boolean Push Button control.
    This control is located on the Controls palette under Boolean.
  7. Rename the control as Acquire.
  8. Create a Boolean LED indicator.
    This indicator is located on the Controls palette under Boolean.
  9. Rename the indicator as Input Overflow.
  10. On the LabVIEW block diagram, drag the Acquire control and the Input Overflow indicator into the While Loop.
    Your block diagram should now look like the following figure.
    Figure 12. My Simple Spectrum Analyzer (FPGA) VI Block Diagram


  11. Place a Write Accessor node in the While Loop to the right of the Acquire control.
    The Write Accessor node is located on the Functions palette under NI-5640R Asynchronous Programming.
  12. Wire the Acquire control to the Write Accessor node.
  13. Wire the Write Accessor node to the start trigger parameter on the ADC node.
  14. Place a Read Accessor node inside the While Loop to the left of the overflow indicator on the ADC node.
    The Read Accessor node is located on the Functions palette under NI-5640R Asynchronous Programming.
  15. Wire the overflow indicator on the ADC node to the Read Accessor node.
  16. Wire the Read Accessor node to the Input Overflow indicator.
  17. Place a DMA to Host node outside the While Loop to the right of the ADC node.
    The DMA to Host node is located on the Functions palette under NI-5640R Asynchronous Programming.
  18. Click the DMA FIFO glyph on the DMA to Host node to launch the Configure Target to Host dialog box and make the changes shown in the following figure.
    Figure 13. Configure Target to Host DMA Dialog Box


  19. Wire the ADC I/Q Data terminal to the data in parameter of the DMA to Host node.
  20. Enable the clock domain terminal of the DMA to Host node by right-clicking the node and selecting Add Clock Domain Terminal.
  21. Wire the I/Q Clk terminal to the clock domain parameter of the DMA to Host node.
    Your block diagram should now look like the following figure.
    Figure 14. Completed FPGA VI Block Diagram Using NI-5640R Asynchronous Programming Palette


  22. Save the VI and the project.
Your FPGA VI is now complete using the NI-5640R Asynchronous Programming palette.
Refer to the Compiling the FPGA VI section for the next steps you should take.