PXIe-5164 FPGA I/O Methods

Note This functionality is only available when using instrument design libraries.
Name Description Clock Domain
Device Registers Function used to read and write registers in the fixed portions of the design. These methods are intended for use only by the instrument design libraries. Use of this method outside of the instrument design libraries may result in aberrant behavior. Clock domain is 40 MHz Onboard Clock. Any

PFI Trigger I/O Methods

Name Description Clock Domain
Set Output Data Writes a boolean to the digital line without enabling the line. Any
Set Output Enable Determines whether the digital line reads external data or writes output. Wiring TRUE to Set Output Enable allows the digital line to write data. Wiring FALSE to Set Output Enable allows the digital line to read external data. Any