Timing and Triggering

This section contains information about timing and triggering for the PXIe-4309.

Sample Clock Timebase

The PXIe-4309 sample clock is derived from the onboard 100 MHz clock, which can be locked to the PXIe backplane clock to synchronize multiple modules.

External Clock

The PXIe-4309 sample clock can be driven from external sources by PXI_TRIG<0..7>, PFI<0..1>, PXI_STAR, or PXIe_DSTAR<A,B>.

Note When using the external sample clock, the PXIe-4309 does not support averaging, auto zero, or chopping.

Digital Triggering

The PXIe-4309 supports acquisition start in response to a digital trigger signal from one of the PXI Express backplane trigger lines or the PFI from the front connector. The trigger circuit can respond either to a rising or a falling edge.