The PXIe-1092 chassis supplies PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 to every peripheral slot with an independent driver for each signal. The following figure shows the chassis reference clock architecture.

Figure 12. Chassis Reference Clock Architecture


Note Dotted line connections are available only with the Timing and Synchronization upgrade.

An independent buffer (having a source impedance matched to the backplane and a skew of less than 250 ps between slots) drives PXI_CLK10 to each slot. You can use this common reference clock signal to synchronize multiple modules in a measurement or control system.

An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched in skew to less than 100 ps. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair to that slot. Refer to the following figure for a termination example.

An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal being driven on the pair to that slot.

In summary, PXI_CLK10 is driven to every slot. PXIe_CLK100 and PXIe_SYNC100 are driven to every peripheral slot.

PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship described in the following figure.

Figure 13. System Reference Clock Default Behavior


By default PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 are synchronized to a calibrated 100 MHz VCXO on the backplane. If the Timing and Synchronization upgrade is present, the backplane 100 MHz VCXO will be locked to a 10 MHz OCXO for improved accuracy and frequency stability. Refer to the chassis specifications for more detailed information.

To synchronize the system to an external clock, you can drive PXI_CLK10 from an external source through the PXI_CLK10_IN pin on the System Timing Slot, or from an external SMA connector on the rear of the chassis (Timing and Synchronization upgrade). When an external clock is detected, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the PXIe-1092 Specifications section for the specification information for an external clock provided on the PXI_CLK10_IN pin of the System Timing Slot or rear panel SMA. If no external clock is detected, with the Timing and Synchronization upgrade, the backplane will default to the onboard calibrated VCXO or OCXO. If an external clock is detected on the rear of the chassis and no clock is detected on the System Timing Slot PXI_CLK10_IN pin, the backplane will lock its VCXO to the clock present on the rear of the chassis. If a clock is detected on the System Timings Slot PXI_CLK10_IN pin, the backplane will lock to this clock regardless of whether or not a clock is present on the rear panel.