IMAQ FPGA RGBToColor VI
- Updated2023-02-21
- 7 minute(s) read
Requires: NI Vision Development Module FPGA
Converts an RGB color value into another format.
IMAQ FPGA RGB32ToHSL32
Converts RGB color values into HSL color values.
Supported Image Types
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RGB32 In specifies the input color values.
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Offset adds an offset to the calculated Hue value when Color Mode is set to HSL. The offset represents the angle by which the hue plane is rotated. Offset can range from 0 to 360. The default offset value of 0 results in a hue value of 0 for the color red (R=255, G=0, B=0). By changing the offset value, you can specify the RGB color that maps to a hue value of 0. When you want to analyze red or colors close to red in the HSL space, you can add an offset so that the hue values associated with these colors are not zero. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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HSL32 Out specifies the output color values.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA RGB32ToHSL32 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3229
- Slice LUTs: 4222
- DSP48s: 15
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 3112
- Slice LUTs: 3619
- DSP48s: 27
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3482
- Slice LUTs: 4542
- DSP48s: 20
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1352
- Slice LUTs: 1799
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
IMAQ FPGA RGB32ToHSL32 x8
Converts RGB color values into HSL color values.
Supported Image Types
|
RGB32 In specifies the input color values.
|
||||||||
|
Offset adds an offset to the calculated Hue value when Color Mode is set to HSL. The offset represents the angle by which the hue plane is rotated. Offset can range from 0 to 360. The default offset value of 0 results in a hue value of 0 for the color red (R=255, G=0, B=0). By changing the offset value, you can specify the RGB color that maps to a hue value of 0. When you want to analyze red or colors close to red in the HSL space, you can add an offset so that the hue values associated with these colors are not zero. |
||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||
|
HSL32 Out specifies the output color values.
|
||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA RGB32ToHSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 18794
- Slice LUTs: 28890
- DSP48s: 96
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 32
- Initiation Interval: 1