IMAQ FPGA Quantify VI
- Updated2023-02-21
- 10 minute(s) read
Requires: NI Vision Development Module FPGA
Quantifies the contents of an image or the regions within an image. The region definition is performed with a labeled image mask. Each region of the mask has a single unique value.
IMAQ FPGA Quantify U8x1
Quantifies the contents of an image or the regions within an image. The region definition is performed with a labeled image mask. Each region of the mask has a single unique value.
Supported Image Types

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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Mask Pixel Bus In is a labeled version of the source image that specifies the regions to quantify. Only the pixels in the original image that correspond to an equivalent pixel in the mask different from 0 are used for the quantification. Each pixel in the image mask indicates, by its value, which region belongs to the corresponding pixel in Image. Up to 255 different regions for an 8-bit image, or 65,535 regions for a 16-bit image, can be quantified directly from the image. A quantification is performed on the complete image if the Mask Pixel Bus is not connected.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Report is a cluster containing the quantification data relative to all the regions within an image, or to the entire image if Mask Pixel Bus In is not connected. This cluster contains the following elements:
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Quantify U8x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3980
- Slice LUTs: 5709
- DSP48s: 2
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 31
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 4063
- Slice LUTs: 5901
- DSP48s: 2
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 31
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3839
- Slice LUTs: 4858
- DSP48s: 4
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 22
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2198
- Slice LUTs: 2719
- DSP48s: 2
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 22
- Initiation Interval: 1
IMAQ FPGA Quantify U16x1
Quantifies the contents of an image or the regions within an image. The region definition is performed with a labeled image mask. Each region of the mask has a single unique value.
Supported Image Types

![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||
![]() |
Mask Pixel Bus In is a labeled version of the source image that specifies the regions to quantify. Only the pixels in the original image that correspond to an equivalent pixel in the mask different from 0 are used for the quantification. Each pixel in the image mask indicates, by its value, which region belongs to the corresponding pixel in Image. Up to 255 different regions for an 8-bit image, or 65,535 regions for a 16-bit image, can be quantified directly from the image. A quantification is performed on the complete image if the Mask Pixel Bus is not connected.
|
||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||
![]() |
Report is a cluster containing the quantification data relative to all the regions within an image, or to the entire image if Mask Pixel Bus In is not connected. This cluster contains the following elements:
|
||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Quantify U16x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 5234
- Slice LUTs: 7158
- DSP48s: 3
- Block RAMs: 11
Estimated Performance
- Minimum Latency: 39
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 5217
- Slice LUTs: 6885
- DSP48s: 5
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 39
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 5354
- Slice LUTs: 6387
- DSP48s: 4
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 28
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2313
- Slice LUTs: 2865
- DSP48s: 2
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 28
- Initiation Interval: 1










