IMAQ FPGA NthOrder VI
- Updated2023-02-21
- 47 minute(s) read
Requires: NI Vision Development Module FPGA
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number. Refer to the NI Vision Concepts Help for more information about the Nth order filter.
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Note This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency.
Total Latency = Minimum Latency + (Image Width+2)((Kernel Size/2) - 0.5) + 3 |
IMAQ FPGA NthOrder 3x3 NoMask U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
 |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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 |
Order is the order number chosen after classing the values. The default is 4. |
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 |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
 |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 3x3 NoMask U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1316
- Slice LUTs: 1633
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1332
- Slice LUTs: 1662
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1643
- Slice LUTs: 1667
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1586
- Slice LUTs: 1625
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA NthOrder 3x3 NoMask U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 3x3 NoMask U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1355
- Slice LUTs: 1948
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1348
- Slice LUTs: 1858
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1683
- Slice LUTs: 1751
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2451
- Slice LUTs: 2515
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA NthOrder 5x5 NoMask U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 5x5 NoMask U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2457
- Slice LUTs: 5440
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2649
- Slice LUTs: 5480
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3028
- Slice LUTs: 5778
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2914
- Slice LUTs: 5983
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA NthOrder 5x5 NoMask U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 5x5 NoMask U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2516
- Slice LUTs: 6326
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2695
- Slice LUTs: 5843
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3406
- Slice LUTs: 6720
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 4959
- Slice LUTs: 9689
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA NthOrder 7x7 NoMask U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 7x7 NoMask U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 4767
- Slice LUTs: 15865
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 6321
- Slice LUTs: 16896
- DSP48s: 0
- Block RAMs: 18
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 5272
- Slice LUTs: 16853
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 13
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 5045
- Slice LUTs: 16719
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 13
- Initiation Interval: 1
IMAQ FPGA NthOrder 7x7 NoMask U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 7x7 NoMask U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 8224
- Slice LUTs: 22889
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 8195
- Slice LUTs: 23354
- DSP48s: 0
- Block RAMs: 36
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 8840
- Slice LUTs: 31207
- DSP48s: 0
- Block RAMs: 18
Estimated Performance
- Minimum Latency: 13
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 6650
- Slice LUTs: 30428
- DSP48s: 0
- Block RAMs: 15
Estimated Performance
- Minimum Latency: 13
- Initiation Interval: 1
IMAQ FPGA NthOrder 3x3 U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 3x3 U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1551
- Slice LUTs: 1937
- DSP48s: 0
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1556
- Slice LUTs: 1884
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1884
- Slice LUTs: 1769
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 3657
- Slice LUTs: 3474
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA NthOrder 3x3 U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 3x3 U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2271
- Slice LUTs: 2668
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2280
- Slice LUTs: 2673
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 2780
- Slice LUTs: 2704
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2725
- Slice LUTs: 2604
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA NthOrder 5x5 U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 5x5 U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2873
- Slice LUTs: 5637
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 3147
- Slice LUTs: 6368
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3278
- Slice LUTs: 5639
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 6334
- Slice LUTs: 11183
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
IMAQ FPGA NthOrder 5x5 U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 5x5 U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 4425
- Slice LUTs: 7954
- DSP48s: 0
- Block RAMs: 11
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 4923
- Slice LUTs: 8147
- DSP48s: 0
- Block RAMs: 26
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 5329
- Slice LUTs: 9147
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 5218
- Slice LUTs: 9290
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
IMAQ FPGA NthOrder 7x7 U8x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
|
||||||||||
|
Order is the order number chosen after classing the values. The default is 4. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA NthOrder 7x7 U8x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 5109
- Slice LUTs: 16684
- DSP48s: 0
- Block RAMs: 11
Estimated Performance
- Minimum Latency: 24
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 7685
- Slice LUTs: 23285
- DSP48s: 0
- Block RAMs: 23
Estimated Performance
- Minimum Latency: 24
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 5628
- Slice LUTs: 17270
- DSP48s: 0
- Block RAMs: 11
Estimated Performance
- Minimum Latency: 21
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 541
- Slice LUTs: 1797
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 21
- Initiation Interval: 1
IMAQ FPGA NthOrder 7x7 U16x1
Orders, or classifies, the pixel values surrounding the pixel being processed. The data is placed into an array and the pixel being processed is set to the nth pixel value, the nth pixel being the ordered number.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.
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Order is the order number chosen after classing the values. The default is 4. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA NthOrder 7x7 U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 8600
- Slice LUTs: 24076
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 24
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 11962
- Slice LUTs: 24777
- DSP48s: 0
- Block RAMs: 39
Estimated Performance
- Minimum Latency: 24
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 9223
- Slice LUTs: 33019
- DSP48s: 0
- Block RAMs: 20
Estimated Performance
- Minimum Latency: 21
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 9001
- Slice LUTs: 33637
- DSP48s: 0
- Block RAMs: 21
Estimated Performance
- Minimum Latency: 21
- Initiation Interval: 1