IMAQ FPGA LinearAverages VI
- Updated2023-02-21
- 43 minute(s) read
Requires: NI Vision Development Module FPGA
Computes the average pixel intensity (mean line profile) on the whole or part of the image.
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Note This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency.
Total Latency = Minimum Latency + (Image Width + 1) x Image Height + 1 |
IMAQ FPGA LinearAverages X U8x1
Calculates the linear average along each column in the image.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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X Resolution is the horizontal resolution of the image. |
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Y Resolution is the vertical resolution of the image. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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 |
X Axis Average is the linear average along each column in the image. |
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 |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 887
- Slice LUTs: 1241
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 906
- Slice LUTs: 1383
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1027
- Slice LUTs: 981
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1005
- Slice LUTs: 951
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
IMAQ FPGA LinearAverages X U8x8
Calculates the linear average along each column in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X Axis Average is the linear average along each column in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2058
- Slice LUTs: 2776
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
IMAQ FPGA LinearAverages Y U8x1
Calculates the linear average along each row in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Y Axis Average is the linear average along each row in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages Y U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 953
- Slice LUTs: 1305
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 972
- Slice LUTs: 1465
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1085
- Slice LUTs: 1034
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 5312
- Slice LUTs: 5028
- DSP48s: 0
- Block RAMs: 25
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
IMAQ FPGA LinearAverages Y U8x8
Calculates the linear average along each row in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Y Axis Average is the linear average along each row in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages Y U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1116
- Slice LUTs: 1333
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA LinearAverages X U16x1
Calculates the linear average along each column in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X Axis Average is the linear average along each column in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1152
- Slice LUTs: 1638
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1177
- Slice LUTs: 1837
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1290
- Slice LUTs: 1262
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1267
- Slice LUTs: 1245
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
IMAQ FPGA LinearAverages X U16x8
Calculates the linear average along each column in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X Axis Average is the linear average along each column in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2657
- Slice LUTs: 3396
- DSP48s: 0
- Block RAMs: 8
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
IMAQ FPGA LinearAverages Y U16x1
Calculates the linear average along each row in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Y Axis Average is the linear average along each row in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages Y U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1218
- Slice LUTs: 1674
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1241
- Slice LUTs: 1882
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1340
- Slice LUTs: 1324
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1317
- Slice LUTs: 1308
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
IMAQ FPGA LinearAverages Y U16x8
Calculates the linear average along each row in the image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Y Axis Average is the linear average along each row in the image. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages Y U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1454
- Slice LUTs: 1729
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
IMAQ FPGA LinearAverages X-Y U8x1
Calculates the linear average along each diagonal running from too-left to bottom-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X-Y Axis Average is the linear average along each diagonal running from top-left to bottom-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X-Y U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1004
- Slice LUTs: 1431
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1036
- Slice LUTs: 1590
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1102
- Slice LUTs: 1144
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1084
- Slice LUTs: 1125
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
IMAQ FPGA LinearAverages X-Y U8x8
Calculates the linear average along each diagonal running from too-left to bottom-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X-Y Axis Average is the linear average along each diagonal running from top-left to bottom-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X-Y U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 4486
- Slice LUTs: 4389
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
IMAQ FPGA LinearAverages X-Y U16x1
Calculates the linear average along each diagonal running from too-left to bottom-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X-Y Axis Average is the linear average along each diagonal running from top-left to bottom-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X-Y U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1269
- Slice LUTs: 1827
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1305
- Slice LUTs: 1795
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1356
- Slice LUTs: 1439
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1338
- Slice LUTs: 1426
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
IMAQ FPGA LinearAverages X-Y U16x8
Calculates the linear average along each diagonal running from too-left to bottom-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X-Y Axis Average is the linear average along each diagonal running from top-left to bottom-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X-Y U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 5661
- Slice LUTs: 5323
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 26
- Initiation Interval: 1
IMAQ FPGA LinearAverages X+Y U8x1
Calculates the linear average along each diagonal running from bottom-left to top-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X+Y Axis Average is the linear average along each diagonal running from bottom-left to top-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X+Y U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 968
- Slice LUTs: 1411
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1000
- Slice LUTs: 1531
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1104
- Slice LUTs: 1107
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1102
- Slice LUTs: 1082
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 12
- Initiation Interval: 1
IMAQ FPGA LinearAverages X+Y U8x8
Calculates the linear average along each diagonal running from bottom-left to top-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X+Y Axis Average is the linear average along each diagonal running from bottom-left to top-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X+Y U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 4471
- Slice LUTs: 4397
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
IMAQ FPGA LinearAverages X+Y U16x1
Calculates the linear average along each diagonal running from bottom-left to top-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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|
X Resolution is the horizontal resolution of the image. |
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|
Y Resolution is the vertical resolution of the image. |
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|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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|
X+Y Axis Average is the linear average along each diagonal running from bottom-left to top-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X+Y U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1233
- Slice LUTs: 1808
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1269
- Slice LUTs: 1786
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1358
- Slice LUTs: 1388
- DSP48s: 0
- Block RAMs: 7
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1340
- Slice LUTs: 1378
- DSP48s: 0
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
IMAQ FPGA LinearAverages X+Y U16x8
Calculates the linear average along each diagonal running from bottom-left to top-right.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
X Resolution is the horizontal resolution of the image. |
||||||||||
|
Y Resolution is the vertical resolution of the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
X+Y Axis Average is the linear average along each diagonal running from bottom-left to top-right. |
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA LinearAverages X+Y U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 5646
- Slice LUTs: 5372
- DSP48s: 0
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 26
- Initiation Interval: 1