NI Vision for LabVIEW

IMAQ FPGA Inverse VI

  • Updated2023-02-21
  • 14 minute(s) read
Owning Palette: Processing
Requires: NI Vision Development Module FPGA

Inverts the pixel intensities of an image to compute the negative of an image.

IMAQ FPGA Inverse U8 x1

Inverts the pixel intensities of an image to compute the negative of an image.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Inverse U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Inverse U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 132
  • Slice LUTs: 114
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 133
  • Slice LUTs: 111
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 132
  • Slice LUTs: 100
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 132
  • Slice LUTs: 95
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

IMAQ FPGA Inverse U8 x8

Inverts the pixel intensities of an image to compute the negative of an image.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Inverse U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Inverse U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 403
  • Slice LUTs: 302
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

IMAQ FPGA Inverse U16 x1

Inverts the pixel intensities of an image to compute the negative of an image.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Inverse U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cu16.gif

Max. Value specifies the maximum intensity pixel value to invert.

cu16.gif

Min. Value specifies the minimum intensity pixel value to invert.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Inverse U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 203
  • Slice LUTs: 221
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 202
  • Slice LUTs: 222
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 203
  • Slice LUTs: 201
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 203
  • Slice LUTs: 220
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1

IMAQ FPGA Inverse U16 x8

Inverts the pixel intensities of an image to compute the negative of an image.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Inverse U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cu16.gif

Max. Value specifies the maximum intensity pixel value to invert.

cu16.gif

Min. Value specifies the minimum intensity pixel value to invert.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Inverse U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 698
  • Slice LUTs: 1073
  • DSP48s: 0
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 1
  • Initiation Interval: 1