IMAQ FPGA IntegerToColorValue VI
- Updated2023-02-21
- 10 minute(s) read
Requires: NI Vision Development Module FPGA
Converts colors in the form of an unsigned 32-bit integer into the three colors in the mode.
IMAQ FPGA IntegerToRGB32
Converts colors in the form of an unsigned 32-bit integer into RGB values.

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U32 Value is a color value encoded as an unsigned 32-bit integer. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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RGB32 Out contains the output color values.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA IntegerToRGB32 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 106
- Slice LUTs: 96
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 106
- Slice LUTs: 94
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 106
- Slice LUTs: 77
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 278
- Slice LUTs: 223
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA IntegerToRGB32 x8
Converts colors in the form of an unsigned 32-bit integer into RGB values.

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U32 Value is a color value encoded as an unsigned 32-bit integer. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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![]() |
RGB32 Out contains the output color values.
|
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![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA IntegerToRGB32 x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1136
- Slice LUTs: 640
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA IntegerToHSL32
Converts colors in the form of an unsigned 32-bit integer into RGB values.

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U32 Value is a color value encoded as an unsigned 32-bit integer. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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Color Value contains the output color values.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA IntegerToHSL32 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2813
- Slice LUTs: 3792
- DSP48s: 15
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2801
- Slice LUTs: 3268
- DSP48s: 27
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3418
- Slice LUTs: 4412
- DSP48s: 20
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1326
- Slice LUTs: 1744
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
IMAQ FPGA IntegerToHSL32x8
Converts colors in the form of an unsigned 32-bit integer into RGB values.

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U32 Value is a color value encoded as an unsigned 32-bit integer. |
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![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||
![]() |
Color Value contains the output color values.
|
||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA IntegerToHSL32x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 18745
- Slice LUTs: 28823
- DSP48s: 96
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 32
- Initiation Interval: 1





