NI Vision for LabVIEW

IMAQ FPGA Gray Morphology VI

  • Updated2023-02-21
  • 215 minute(s) read
Owning Palette: Morphology
Requires: NI Vision Development Module FPGA

Performs grayscale morphological transformations.

Note  

This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency.

For the Erosion and Dilation x1 VI instances, use this formula to calculate the total latency.

  • Total Latency = Minimum Latency + (Image Width + 1)((Kernel Size/2) - 0.5) + Kernel Size

For the Open and Close x1 VI instances, use this formula to calculate the total latency.

  • Total Latency = Minimum Latency + 2*((Image Width+2)((Kernel Size/2) - 0.5) + 3)

For the Erosion and Dilation x8 VI instances, use this formula to calculate the total latency.

  • Total Latency = Minimum Latency + Floor(Image Width/8)((Kernel Size/2) - 0.5) + 2

For the Open and Close x8 VI instances, use this formula to calculate the total latency.

  • Total Latency = Minimum Latency + 2*(Floor(Image Width/8)((Kernel Size/2) - 0.5) + 2)

IMAQ FPGA GrayMorphology Erosion 3x3 U8x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 3x3 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 3x3 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1100
  • Slice LUTs: 1055
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1107
  • Slice LUTs: 1176
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 984
  • Slice LUTs: 540
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2345
  • Slice LUTs: 1595
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 3x3 U8x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 3x3 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 3x3 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2520
  • Slice LUTs: 2878
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 3x3 U8x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 3x3 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 3x3 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2185
  • Slice LUTs: 2028
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2188
  • Slice LUTs: 1822
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2313
  • Slice LUTs: 1677
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2345
  • Slice LUTs: 1582
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 3x3 U8x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 3x3 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 3x3 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2520
  • Slice LUTs: 2884
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 3x3 U8x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 3x3 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 3x3 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 3118
  • Slice LUTs: 2936
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 3118
  • Slice LUTs: 2667
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3305
  • Slice LUTs: 2312
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4306
  • Slice LUTs: 2797
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 3x3 U8x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 3x3 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 3x3 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4564
  • Slice LUTs: 5365
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 3x3 U8x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 3x3 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 3x3 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 3118
  • Slice LUTs: 2943
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 3119
  • Slice LUTs: 2693
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3305
  • Slice LUTs: 2317
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4306
  • Slice LUTs: 2804
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 3x3 U8x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 3x3 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 3x3 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4564
  • Slice LUTs: 5364
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 5x5 U8x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 5x5 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 5x5 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2420
  • Slice LUTs: 2017
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2437
  • Slice LUTs: 2350
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1908
  • Slice LUTs: 990
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4567
  • Slice LUTs: 2862
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 5x5 U8x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 5x5 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 5x5 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6344
  • Slice LUTs: 4214
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 5x5 U8x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 5x5 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 5x5 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2420
  • Slice LUTs: 2107
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2419
  • Slice LUTs: 2156
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1908
  • Slice LUTs: 980
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4567
  • Slice LUTs: 2868
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 5x5 U8x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 5x5 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 5x5 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6344
  • Slice LUTs: 4348
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 5x5 U8x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 5x5 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 5x5 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 4616
  • Slice LUTs: 3966
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 33
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 4634
  • Slice LUTs: 4446
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 33
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 4273
  • Slice LUTs: 2515
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 8600
  • Slice LUTs: 5141
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 5x5 U8x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 5x5 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 5x5 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 12104
  • Slice LUTs: 8093
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 5x5 U8x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 5x5 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 5x5 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 4616
  • Slice LUTs: 3961
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 33
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 4634
  • Slice LUTs: 4293
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 33
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 4273
  • Slice LUTs: 2524
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 8600
  • Slice LUTs: 5139
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 5x5 U8x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 5x5 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 5x5 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 12104
  • Slice LUTs: 8076
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 7x7 U8x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 7x7 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 7x7 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 4234
  • Slice LUTs: 3368
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 25
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 4273
  • Slice LUTs: 4022
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 25
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3253
  • Slice LUTs: 1457
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4004
  • Slice LUTs: 2406
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 7x7 U8x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 7x7 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 7x7 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 10733
  • Slice LUTs: 7039
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 7x7 U8x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 7x7 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 7x7 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 4234
  • Slice LUTs: 3565
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 25
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 4230
  • Slice LUTs: 3387
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 25
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3253
  • Slice LUTs: 1483
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4004
  • Slice LUTs: 2412
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 7x7 U8x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 7x7 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 7x7 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 10733
  • Slice LUTs: 6954
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 7x7 U8x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 7x7 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 7x7 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 8073
  • Slice LUTs: 6716
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 49
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 8070
  • Slice LUTs: 7403
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 49
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 7759
  • Slice LUTs: 4492
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 7537
  • Slice LUTs: 4281
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 7x7 U8x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 7x7 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 7x7 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 20677
  • Slice LUTs: 13551
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 7x7 U8x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 7x7 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 7x7 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 8073
  • Slice LUTs: 6714
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 49
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 8070
  • Slice LUTs: 7516
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 49
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 7759
  • Slice LUTs: 4468
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 7537
  • Slice LUTs: 4281
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 7x7 U8x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 7x7 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 7x7 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 20676
  • Slice LUTs: 13383
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 9x9 U8x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 9x9 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 9x9 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 6679
  • Slice LUTs: 5561
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 6682
  • Slice LUTs: 5607
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 6076
  • Slice LUTs: 3375
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 30
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1533
  • Slice LUTs: 893
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 30
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 9x9 U8x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 9x9 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 9x9 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 18355
  • Slice LUTs: 10354
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 9x9 U8x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 9x9 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 9x9 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 6682
  • Slice LUTs: 5881
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 6679
  • Slice LUTs: 5609
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 6043
  • Slice LUTs: 3402
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 30
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1525
  • Slice LUTs: 899
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 30
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 9x9 U8x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 9x9 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 9x9 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 18343
  • Slice LUTs: 10599
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 9x9 U8x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 9x9 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 9x9 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 12904
  • Slice LUTs: 11176
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 69
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 12901
  • Slice LUTs: 9913
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 69
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 11895
  • Slice LUTs: 6877
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 59
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1168
  • Slice LUTs: 668
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 59
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 9x9 U8x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 9x9 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 9x9 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 35895
  • Slice LUTs: 20126
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close9x9 U8x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close9x9 U8x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close9x9 U8x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 12904
  • Slice LUTs: 11162
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 69
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 12901
  • Slice LUTs: 9984
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 69
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 11895
  • Slice LUTs: 6857
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 59
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2910
  • Slice LUTs: 1686
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 59
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close9x9 U8x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close9x9 U8x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close9x9 U8x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 35877
  • Slice LUTs: 20398
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 3x3 U16x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 3x3 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 3x3 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1694
  • Slice LUTs: 1571
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1697
  • Slice LUTs: 1309
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1776
  • Slice LUTs: 1031
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1789
  • Slice LUTs: 1090
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 3x3 U16x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 3x3 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 3x3 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 5420
  • Slice LUTs: 4598
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 3x3 U16x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 3x3 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 3x3 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 3769
  • Slice LUTs: 3197
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 3769
  • Slice LUTs: 3111
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3857
  • Slice LUTs: 2483
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1789
  • Slice LUTs: 1088
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 3x3 U16x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 3x3 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 3x3 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4377
  • Slice LUTs: 5102
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 3x3 U16x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 3x3 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 3x3 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 5248
  • Slice LUTs: 4572
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 5248
  • Slice LUTs: 3999
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 5417
  • Slice LUTs: 3400
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3338
  • Slice LUTs: 2000
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 3x3 U16x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 3x3 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 3x3 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 9049
  • Slice LUTs: 9051
  • DSP48s: 0
  • Block RAMs: 15

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 3x3 U16x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 3x3 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 3x3 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 5248
  • Slice LUTs: 4587
  • DSP48s: 0
  • Block RAMs: 9

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 5250
  • Slice LUTs: 4388
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 5417
  • Slice LUTs: 3376
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3338
  • Slice LUTs: 2000
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 3x3 U16x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 3x3 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 3x3 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 9049
  • Slice LUTs: 9053
  • DSP48s: 0
  • Block RAMs: 15

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 5x5 U16x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 5x5 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 5x5 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 4195
  • Slice LUTs: 3559
  • DSP48s: 0
  • Block RAMs: 11

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 4196
  • Slice LUTs: 3266
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 3853
  • Slice LUTs: 2101
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 15
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3881
  • Slice LUTs: 2225
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 15
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 5x5 U16x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 5x5 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 5x5 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 13409
  • Slice LUTs: 8034
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 5x5 U16x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 5x5 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 5x5 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 11040
  • Slice LUTs: 9302
  • DSP48s: 0
  • Block RAMs: 10

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 11038
  • Slice LUTs: 8182
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 10578
  • Slice LUTs: 6073
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 15
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3881
  • Slice LUTs: 2227
  • DSP48s: 0
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 15
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 5x5 U16x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 5x5 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 5x5 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 10351
  • Slice LUTs: 9085
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 5x5 U16x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 5x5 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 5x5 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 14947
  • Slice LUTs: 12637
  • DSP48s: 0
  • Block RAMs: 19

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 14946
  • Slice LUTs: 10879
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 14142
  • Slice LUTs: 8025
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 29
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 7425
  • Slice LUTs: 4202
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 29
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 5x5 U16x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 5x5 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 5x5 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 22884
  • Slice LUTs: 16290
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 5x5 U16x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 5x5 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 5x5 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 14947
  • Slice LUTs: 12736
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 14946
  • Slice LUTs: 10919
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 35
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 14142
  • Slice LUTs: 8022
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 29
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 7425
  • Slice LUTs: 4208
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 29
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 5x5 U16x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 5x5 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 5x5 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 22880
  • Slice LUTs: 16162
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 23
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 7x7 U16x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 7x7 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 7x7 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 7627
  • Slice LUTs: 6361
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 28
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 7624
  • Slice LUTs: 5756
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 28
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 7130
  • Slice LUTs: 4196
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6908
  • Slice LUTs: 4001
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 7x7 U16x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 7x7 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 7x7 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 25464
  • Slice LUTs: 13187
  • DSP48s: 0
  • Block RAMs: 32

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 7x7 U16x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 7x7 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 7x7 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 7627
  • Slice LUTs: 6335
  • DSP48s: 0
  • Block RAMs: 13

Estimated Performance

  • Minimum Latency: 28
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 7624
  • Slice LUTs: 5802
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 28
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 6854
  • Slice LUTs: 3619
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6908
  • Slice LUTs: 3837
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 7x7 U16x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 7x7 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 7x7 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 23411
  • Slice LUTs: 13187
  • DSP48s: 0
  • Block RAMs: 32

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 7x7 U16x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 7x7 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 7x7 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 14829
  • Slice LUTs: 12427
  • DSP48s: 0
  • Block RAMs: 29

Estimated Performance

  • Minimum Latency: 55
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 14826
  • Slice LUTs: 10424
  • DSP48s: 0
  • Block RAMs: 72

Estimated Performance

  • Minimum Latency: 55
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 13525
  • Slice LUTs: 7805
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 13303
  • Slice LUTs: 7578
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 7x7 U16x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 7x7 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 7x7 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 47768
  • Slice LUTs: 25521
  • DSP48s: 0
  • Block RAMs: 63

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 7x7 U16x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 7x7 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 7x7 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 14829
  • Slice LUTs: 12432
  • DSP48s: 0
  • Block RAMs: 28

Estimated Performance

  • Minimum Latency: 55
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 14826
  • Slice LUTs: 9995
  • DSP48s: 0
  • Block RAMs: 72

Estimated Performance

  • Minimum Latency: 55
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 13525
  • Slice LUTs: 7681
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 13303
  • Slice LUTs: 7443
  • DSP48s: 0
  • Block RAMs: 36

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 7x7 U16x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 7x7 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 7x7 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 47767
  • Slice LUTs: 25645
  • DSP48s: 0
  • Block RAMs: 63

Estimated Performance

  • Minimum Latency: 27
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 9x9 U16x1

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 9x9 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 9x9 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 12080
  • Slice LUTs: 10034
  • DSP48s: 0
  • Block RAMs: 18

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 12077
  • Slice LUTs: 9114
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 11028
  • Slice LUTs: 6806
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 10806
  • Slice LUTs: 6558
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Erosion 9x9 U16x8

Performs an erosion, which eliminates isolated background pixels.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Erosion 9x9 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Erosion 9x9 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 39434
  • Slice LUTs: 21055
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 9x9 U16x1

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 9x9 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 9x9 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 12079
  • Slice LUTs: 10071
  • DSP48s: 0
  • Block RAMs: 20

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 12076
  • Slice LUTs: 9890
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 41
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 10994
  • Slice LUTs: 6985
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 10772
  • Slice LUTs: 6734
  • DSP48s: 0
  • Block RAMs: 24

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Dilation 9x9 U16x8

Performs a dilation, which eliminates holes isolated in particles.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Dilation 9x9 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Dilation 9x9 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 38146
  • Slice LUTs: 20642
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 9x9 U16x1

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 9x9 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 9x9 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 23670
  • Slice LUTs: 19721
  • DSP48s: 0
  • Block RAMs: 37

Estimated Performance

  • Minimum Latency: 81
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 23667
  • Slice LUTs: 16622
  • DSP48s: 0
  • Block RAMs: 96

Estimated Performance

  • Minimum Latency: 81
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 21203
  • Slice LUTs: 12888
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 61
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 20981
  • Slice LUTs: 12674
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 61
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Open 9x9 U16x8

Performs an erosion followed by a dilation.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Open 9x9 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Open 9x9 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 76446
  • Slice LUTs: 40462
  • DSP48s: 0
  • Block RAMs: 96

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 9x9 U16x1

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 9x9 U16x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 9x9 U16x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 23670
  • Slice LUTs: 19725
  • DSP48s: 0
  • Block RAMs: 38

Estimated Performance

  • Minimum Latency: 75
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 23667
  • Slice LUTs: 17837
  • DSP48s: 0
  • Block RAMs: 96

Estimated Performance

  • Minimum Latency: 75
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 21210
  • Slice LUTs: 13277
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 61
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 20988
  • Slice LUTs: 13009
  • DSP48s: 0
  • Block RAMs: 48

Estimated Performance

  • Minimum Latency: 61
  • Initiation Interval: 1

IMAQ FPGA GrayMorphology Close 9x9 U16x8

Performs a dilation followed by an erosion.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA GrayMorphology Close 9x9 U16x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

c1dbool.gif

Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:

1 2 3
4 5 6
7 8 9

Transpose to:

1 4 7
2 5 8
3 6 9

Convert to 1D array:

1 4 7 2 5 8 3 6 9
cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

ibool.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA GrayMorphology Close 9x9 U16x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 76428
  • Slice LUTs: 41061
  • DSP48s: 0
  • Block RAMs: 96

Estimated Performance

  • Minimum Latency: 31
  • Initiation Interval: 1