IMAQ FPGA ExtractColorPlanes VI
- Updated2023-02-21
- 30 minute(s) read
Requires: NI Vision Development Module FPGA
Extracts the three planes from an image.
IMAQ FPGA ExtractColorPlanes RGB32x1
Extracts the RGB planes from an image.
Supported Image Types
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RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Red Plane Out is the reference to the image containing the red plane of the source image.
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Green Plane Out is the reference to the image containing the green plane of the source image.
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Blue Plane Out is the reference to the image containing the blue plane of the source image.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA ExtractColorPlanes RGB32x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 231
- Slice LUTs: 212
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 230
- Slice LUTs: 207
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 231
- Slice LUTs: 178
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 590
- Slice LUTs: 468
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ExtractColorPlanes RGB32x8
Extracts the RGB planes from an image.
Supported Image Types
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RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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|
Red Plane Out is the reference to the image containing the red plane of the source image.
|
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|
Green Plane Out is the reference to the image containing the green plane of the source image.
|
||||||||||||||||||
|
Blue Plane Out is the reference to the image containing the blue plane of the source image.
|
||||||||||||||||||
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ExtractColorPlanes RGB32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1116
- Slice LUTs: 732
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ExtractColorPlanes HSL32x1
Extracts the HSL planes from an image.
Supported Image Types
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RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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Hue Plane Out is the reference to the image containing the hue plane of the source image.
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Sat Plane Out is the reference to the image containing the saturation plane of the source image.
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Lum Plane Out is the reference to the image containing the luminance plane of the source image.
|
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ExtractColorPlanes HSL32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 231
- Slice LUTs: 212
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 230
- Slice LUTs: 208
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 231
- Slice LUTs: 179
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 236
- Slice LUTs: 187
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ExtractColorPlanes HSL32x8
Extracts the HSL planes from an image.
Supported Image Types
|
RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Hue Plane Out is the reference to the image containing the hue plane of the source image.
|
||||||||||||||||||
|
Sat Plane Out is the reference to the image containing the saturation plane of the source image.
|
||||||||||||||||||
|
Lum Plane Out is the reference to the image containing the luminance plane of the source image.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ExtractColorPlanes HSL32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1116
- Slice LUTs: 731
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ExtractColorPlanes RGBToHSL32
Extracts the HSL planes from an image.
Supported Image Types
|
RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Hue Plane Out is the reference to the image containing the hue plane of the source image.
|
||||||||||||||||||
|
Sat Plane Out is the reference to the image containing the saturation plane of the source image.
|
||||||||||||||||||
|
Lum Plane Out is the reference to the image containing the luminance plane of the source image.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ExtractColorPlanes RGBToHSL32 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3295
- Slice LUTs: 4258
- DSP48s: 15
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 3177
- Slice LUTs: 3671
- DSP48s: 27
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3562
- Slice LUTs: 4634
- DSP48s: 20
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1384
- Slice LUTs: 1832
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
IMAQ FPGA ExtractColorPlanes RGBToHSL32 x8
Extracts the HSL planes from an image.
Supported Image Types
|
RGB32 Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Hue Plane Out is the reference to the image containing the hue plane of the source image.
|
||||||||||||||||||
|
Sat Plane Out is the reference to the image containing the saturation plane of the source image.
|
||||||||||||||||||
|
Lum Plane Out is the reference to the image containing the luminance plane of the source image.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ExtractColorPlanes RGBToHSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 17028
- Slice LUTs: 29048
- DSP48s: 96
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 32
- Initiation Interval: 1